Program

Time	Topic	Lecturer
8:30 – 9:00	Event Registration
From 9:00 to 17:30	Introduction to Digital Design Flow	Alejandro Estay
	Verilog for Synthesis	Alejandro Estay
	Lunch Break
	Fundamentals of CMOS I	Alejandro Estay
	Simulation of Digital Circuits with VCS	Alejandro Estay
18:00 – 19:00	Keynote	(TBD)

Time	Topic	Lecturer
From 9:00 to 17:30	Fundamentals of CMOS II	Alejandro Estay
	Lab 1: Verilog	Alejandro Estay
	Lunch Break
	Introduction to Fabrication of ICs	Alejandro Estay
	Lab 2: Verilog	Alejandro Estay
18:00 – 19:00	Keynote	(TBD)

Time	Topic	Lecturer
From 9:00 to 17:30	Design Compiler I	Esteban Viveros
	Design Compiler II	Esteban Viveros
	Lunch Break
	Lab 3: Synthesis with Design Compiler	Esteban Viveros
	Lab 4: Synthesis with Design Compiler	Esteban Viveros
18:00 – 19:00	Keynote	(TBD)

Time	Topic	Lecturer
From 9:00 to 17:30	IC Compiler I	Benjamín Villegas
	IC Compiler II	Benjamín Villegas
	Lunch Break
	Lab 5: Place & Route with IC Compiler	Benjamín Villegas
	Lab 6: Place & Route with IC Compiler	Benjamín Villegas
18:00 – 19:00	Keynote	(TBD)

Time	Topic	Lecturer
From 09:00 to 18:00	Lab 7: Final Review	(TBD)
	Evaluation
	Lunch Break
	TBD
	Event Closure