Lecturers
July 7th – July 11th, 2025
Av. Vicuña Mackenna 3939,
Campus San Joaquín, Edificio K, Piso 3,
Laboratorio K306 Universidad Santa María.
Alejandro Estay
Electronic Engineer from Universidad Católica de Valparaiso (2019). Previous experience in electronic design for electronic warfare and RF. Working as Applications Engineer for Synopsys since 2022, for Formal Verification products. Digital Design Laboratory Instructor at Universidad Tecnica Federico Santa Maria since 2022 and contributing with teaching material since 2020.
Esteban Viveros
Esteban Viveros is an Electronic Engineer from Universidad de Concepción (Concepcion, Chile).
He started to work at Synopsys on December 2013 as Quality Engineer and now he is R&D Manager of a team in Chile Site.
The PV team is part of the Digital Design Group (DDG) and works on the “Product Validation” of the Synopsys tools used for RTL Synthesis, Test, Physical Implementation (Place and Route), Formal Verification and Sign-off.
His team is responsible of the quality of the tools focusing on the stability, performance, usability and QoR (Quality of Results).
The team interacts daily with colleagues and internal/external customers in different parts of the world (mainly US, China and Taiwan).
Besides that, Esteban actively collaborates on the university training activities dictated by Synopsys Chile.
Benjamín Villegas
Benjamín Villegas has a Master of Science (MSc.) in Electronic Engineering with a minor in Computers, from the Universidad Técnica Federico Santa María (UTFSM) in Valparaiso, Chile. He currently works as a product engineer (PE) at Synopsys since March 2024, supporting Power Analysis capabilities of Synthesis and Place & Route tools. While pursuing his master’s degree, he worked as a research assistant with a focus on microelectronic design, RISC-V and System on Chip (SoC) technology. He has also performed research in topics related to data science, machine learning (ML) and Internet of Things (IoT).