Program
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Preliminar Program
Digital Integrated Circuits Design
Digital Integrated Circuits Design
Monday - 20/7/2026
| Time | Topic | Lecturer |
|---|---|---|
| 8:30 – 9:00 | Event Registration | |
| From 9:00 to 17:30 | Introduction to Digital Design Flow | Jose Paredes |
| Coffee Break | ||
| Verilog for Synthesis | Jose Paredes | |
| Lunch Break | ||
| Fundamentals of CMOS I | Jose Paredes | |
| Coffee Break | ||
| Simulation of Digital Circuits with VCS | Jose Paredes | |
| 17:30 – 18:30 | Keynote | (TBD) |
Tuesday - 21/7/2026
| Time | Topic | Lecturer |
|---|---|---|
| From 9:00 to 17:30 | Fundamentals of CMOS II | Jose Paredes |
| Coffee Break | ||
| Lab 1: Verilog | Jose Paredes | |
| Lunch Break | ||
| Introduction to Fabrication of ICs | Jose Paredes | |
| Coffee Break | ||
| Lab 2: Verilog | Jose Paredes | |
| 17:30 – 18:30 | Keynote | (TBD) |
Wednesday - 22/7/2026
| Time | Topic | Lecturer |
|---|---|---|
| From 9:00 to 17:30 | Design Compiler I | (TBD) |
| Coffee Break | ||
| Design Compiler II | (TBD) | |
| Lunch Break | ||
| Lab 3: Synthesis with Design Compiler | (TBD) | |
| Coffee Break | ||
| Lab 4: Synthesis with Design Compiler | (TBD) | |
| 17:30 – 18:30 | Keynote | (TBD) |
Thursday - 23/7/2026
| Time | Topic | Lecturer |
|---|---|---|
| From 9:00 to 17:30 | IC Compiler I | Ronaldo Serrano |
| Coffee Break | ||
| IC Compiler II | Ronaldo Serrano | |
| Lunch Break | ||
| Lab 5: Place & Route with IC Compiler | Ronaldo Serrano | |
| Coffee Break | ||
| Lab 6: Place & Route with IC Compiler | Ronaldo Serrano | |
| 17:30 – 18:30 | Keynote | (TBD) |
Friday - 24/7/2026
| Time | Topic | Lecturer |
|---|---|---|
| From 09:00 to 17:00 | Lab 7: Final Review | Ronaldo Serrano |
| Coffee Break | ||
| Evaluation | ||
| Lunch Break | ||
| TBD | ||
| Coffee Break | ||
| Event Closure |