Lecturers

José Paredes holds a degree in Electronic Engineering from the Universidad San Francisco de Quito (Ecuador). He is currently a Staff Applications Engineer at Synopsys Chile, specializing in semiconductor design methodologies, timing and noise analysis, parasitic extraction, and large-scale design optimization. Throughout his career, he has supported leading semiconductor companies in the deployment and validation of advanced Electronic Design Automation (EDA) flows across technology nodes ranging from 90nm to 2nm. His experience includes transistor-level and gate-level extraction, distributed timing analysis, characterization methodologies, release validation, customer migration support, and the development of scalable solutions for billion-gate-class integrated circuit designs. Prior to joining Synopsys, he worked as a Research Assistant at the Universidad San Francisco de Quito, leading projects in biomedical electronics, FPGA development, and RISC-V-based embedded systems. He has authored and co-authored multiple IEEE publications in biomedical electronics, embedded systems, engineering education, and signal acquisition technologies. His work has contributed to advancements in electromedical device characterization, control systems education, and electromyography-based sensing systems. He received the Synopsys DTG Individual Award 2025 in recognition of his technical contributions and impact within the organization. During his undergraduate studies, he served as Chair of the IEEE Electron Devices Society (EDS) Student Branch Chapter and founded the IEEE Circuits and Systems Society (CAS) and IEEE Robotics and Automation Society (RAS) student chapters at the Universidad San Francisco de Quito, promoting technical development, research collaboration, and engineering education.