Program

Time	Topic	Lecturer
8:30 – 9:00	Event Registration
From 9:00 to 18:00	Introduction to Digital Design Flow	Ronald Valenzuela
	Break
	Verilog for Synthesis	Thomas Krohmer
	Lunch Break
	Lab 1: Verilog	Thomas Krohmer
	Break
	Lab 1: Verilog	Thomas Krohmer
18:00 - 18:30	-

Time	Topic	Lecturer
From 9:00 to 18:00	Fundamentals of CMOS	Ronald Valenzuela
	Break
	Simulation of Digital Circuits w/ Verdi	Thomas Krohmer
	Lunch Break
	Lab 2: Simulation w/ Verdi	Thomas Krohmer
	Break
	Lab 2: Simulation w/ Verdi	Thomas Krohmer
18:00 - 18:30	-

Time	Topic	Lecturer
From 9:00 to 18:00	Design Compiler I	Miguel Durán
	Break
	Design Compiler II	Miguel Durán
	Lunch Break
	Lab 3: Synthesis with Design Compiler	Luciano Radrigan
	Break
	Lab 4: Synthesis with Design Compiler	Luciano Radrigan
18:00 - 18:30	-

Time	Topic	Lecturer
From 9:00 to 18:00	IC Compiler I	Jose Martínez
	Break
	IC Compiler II	Jose Martínez
	Lunch Break
	Lab 5: Place & Route with IC Compiler	Jose Martínez
	Break
	Lab 6: Place & Route with IC Compiler	Jose Martínez
18:00 - 18:30	-

Time	Topic	Lecturer
From 9:00 to 18:00	Working at Synopsys	Ronald Valenzuela
	Break
	Lab 7: Final Review	Jose Martínez
	Lunch Break
	TBD
	TBD
	Event Closure
18:00 - 18:30	-