Lecturers
August 10th – 14th, 2026 | 9:00 AM – 6:00 PM daily
Facultad de Ingeniería,
Universidad de Concepción,
Edmundo Larenas 219, Concepción.
Ronald Valenzuela
Ronald Valenzuela currently manages a team of Product Engineers (PE) at Synopsys. With his team, they provide support on Power Optimization and Power Analysis capabilities of Synthesis and Place & Route tools. As PEs, they engage with customers to enable methodologies and, also contribute to planning and testing of the tools. Ronald has 10 years of experience in EDA Industry, he is Electronics Engineer of Universidad de Concepción and has a certification on Integrated Circuit design from Stanford University, CA.
Thomas Krohmer
Thomas Krohmer has an electronic engineering diploma from Universidad de Concepcion (Chile), focusing on digital circuits and FPGA/VLSI. He is a Staff Engineer supporting Clock Gating and Power Analysis technologies since he joined Synopsys in 2022. He has helped develop and test new features as well as keeping documentation up to date. Thomas has also prepared and presented several trainings to customers.
Miguel Durán
Miguel Durán received his B.Sc. In Electrical Engineering from the Universidad de Concepcion, Chile, in 2021, where he is currently pursuing a PhD. In Electrical Engineering since 2025. He is also a Senior R&D at Synopsys, working on advanced solutions for large-scale design automation in physical synthesis and optimization flows. His research interests span Electronic Design Automation, physical synthesis, high-performance computing, and the integration of machine learning techniques into EDA workflows.
Luciano Radrigán
Luciano Radrigan Figueroa is an Electrical Engineer with a Ph.D. from Universidad de Concepción (Chile), working at the intersection of intelligent systems, embedded hardware, and industrial AI. His experience spans the full electronic stack—from firmware on resource-constrained microcontrollers to deep learning deployed at the edge. He is a Staff Application Engineer at Synopsys, leading digital implementation teams through physical IC design, including synthesis, floorplanning, placement, routing, and timing closure on complex VLSI flows. His research emphasizes practical edge deployment of machine learning, including predictive maintenance informed by finite element and discrete element modeling with Ansys and Rocky DEM, plus TinyML and transfer learning for condition monitoring under real energy, bandwidth, and compute limits across mining, manufacturing, and logistics. As faculty, he teaches Embedded Systems and IoT at Universidad de Chile and contributes to ICT workshops and sensor/condition-monitoring courses at Universidad de Concepción, supervising graduate work on edge AI, cloud-integrated IoT, and industrial computer vision. His combined expertise in VLSI physical design and intelligent embedded systems bridges hardware engineering and AI with both depth and deployability.
José Martínez
José Martínez is an Electrical Engineer with mention in Electronics and Telecommunications, graduated from Universidad de Costa Rica. He holds a master’s degree in Management and Human Resources. José started working at Intel Costa Rica in 2014 where he held different roles such as Structural Designer, focusing on thermal analysis, Product Content Validation, centered in Array MBIST DFT, including the pre-silicon and post-silicon verification, repair methodology for redundant SRAMs, NPI (new product introduction), functional content writer for coverage increase, as well as OSNH (Operative System No-Harm) Engineer, in which he was directly involved in platform validation on different soft/hard reset states, performance, OS and uCode scalability, as well as part of the chip security reactive team. Since 2022 he works at Synopsys Chile. Currently, José is part of the CCSG team working towards PPA (power, performance, area) push; improving customers QoR results in a scalable and reproducible methodology.