Program
Preliminar Program
Digital Integrated Circuit Design
Digital Integrated Circuit Design
Monday - 1/19/2026
| Time | Topic | Lecturer |
|---|---|---|
| 8:30 – 9:00 | Event Registration | |
| From 9:00 to 17:30 | Introduction to Digital Design Flow | Víctor Grimblatt |
| Verilog for Synthesis | Víctor Grimblatt | |
| Lunch Break | ||
| Fundamentals of CMOS I | Víctor Grimblatt | |
| Simulation of Digital Circuits with VCS | Víctor Grimblatt | |
| 17:30 – 18:30 | Keynote | (TBD) |
Tuesday - 1/20/2026
| Time | Topic | Lecturer |
|---|---|---|
| From 9:00 to 17:30 | Fundamentals of CMOS II | Víctor Grimblatt |
| Lab 1: Verilog | Víctor Grimblatt | |
| Lunch Break | ||
| Introduction to Fabrication of ICs | Víctor Grimblatt | |
| Lab 2: Verilog | Víctor Grimblatt | |
| 17:30 – 18:30 | Keynote | (TBD) |
Wednesday - 1/21/2026
| Time | Topic | Lecturer |
|---|---|---|
| From 9:00 to 17:30 | Design Compiler I | Daniel Giraldo |
| Design Compiler II | Daniel Giraldo | |
| Lunch Break | ||
| Lab 3: Synthesis with Design Compiler | Daniel Giraldo | |
| Lab 4: Synthesis with Design Compiler | Daniel Giraldo | |
| 17:30 – 18:30 | Keynote | (TBD) |
Thursday - 1/22/2026
| Time | Topic | Lecturer |
|---|---|---|
| From 9:00 to 17:30 | IC Compiler I | José Martínez |
| IC Compiler II | José Martínez | |
| Lunch Break | ||
| Lab 5: Place & Route with IC Compiler | José Martínez | |
| Lab 6: Place & Route with IC Compiler | José Martínez | |
| 17:30 – 18:30 | Keynote | (TBD) |
Friday - 1/23/2026
| Time | Topic | Lecturer |
|---|---|---|
| From 09:00 to 17:00 | Lab 7: Final Review | (TBD) |
| Evaluation | ||
| Lunch Break | ||
| TBD | ||
| Event Closure |