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Lecturers

January 12th – 16th, 2026 | 9:00 AM – 6:00 PM daily
Tecnológico de Monterrey, Nuevo León
Av. Gral. Ramón Corona No 2514, Colonia Nuevo México, 45201 Zapopan, Jal.

Victor Grimblatt

Victor Grimblatt has an engineering diploma in microelectronics from Institut Nationale Polytechnique de Grenoble (INPG – France) and an electronic engineering diploma from Universidad Tecnica Federico Santa Maria (Chile). He is doing his PhD on IoT for Smart Agriculture at IMS lab, University of Bordeaux. He is currently R&D Group Director and General Manager of Synopsys Chile. He has expertise and knowledge in business and technology and understands very well the trends of the electronic industry; therefore, he is often consulted for new technological business development. He has published several papers in IoT, EDA and embedded systems development, and since 2007 he has been invited to several Latin American Conferences (Argentina, Brazil, Chile, Mexico, Peru and Uruguay) to talk about Circuit Design, EDA, IoT, and Embedded Systems. Since 2012 he is chair of the IEEE Chilean chapter of the CASS. He is also the President of the Chilean Electronic and Electrical Industry Association (AIE). He has been part of several conferences TCP (ISCAS, ICECS, LASCAS) and is chairing the EDA and Circuit design Sub-Committee for ICECS. He is also Program Co-Chair of FoodCAS. Since 2018 he is Chair of LASCAS Steering Committee.

Daniel Giraldo

Daniel is an electronic engineer graduated from the Universidad Industrial de Santander in Colombia. He served as President of the IEEE Student Branch at his university and has 5 years of experience as a Verification/Validation Engineer at Synopsys, providing support to Design Compiler and Fusion Compiler tools, with a focus on synthesis.

He combines experience, technical leadership, and knowledge of Synopsys Synthesis tools, bringing comprehensive perspective to the integrated circuit design and verification process.

José Martinéz

José Martínez is an Electrical Engineer with mention in Electronics and Telecommunications, graduated from Universidad de Costa Rica. He holds a master’s degree in Management and Human Resources. José started working at Intel Costa Rica in 2014 where he held different roles such as Structural Designer, focusing on thermal analysis, Product Content Validation, centered in Array MBIST DFT, including the pre-silicon and post-silicon verification, repair methodology for redundant SRAMs, NPI (new product introduction), functional content writer for coverage increase, as well as OSNH (Operative System NoHarm) Engineer, in which he was directly involved in platform validation on different soft/hard reset states, performance, OS and uCode scalability, as well as part of the chip security reactive team. Since 2022 he works at Synopsys Chile. Currently, José is part of the CCSG team working towards PPA (power, performance, area) push; improving customers QoR results in a scalable and reproducible methodology.