Lecturers
August 11 th - August 15 th , 2025
Tecnológico de México / Instituto Tecnológico de Aguascalientes
Laboratorio de Diseño de Semiconductores y Electrónica Avanzada.
Av. Adolfo López Mateos #1801 Ote.
Fracc. Bona Gens, C.P. 20255
Aguascalientes, Ags., México
Victor Grimblatt has an engineering diploma in microelectronics from Institut Nationale Polytechnique de Grenoble (INPG – France) and an electronic engineering diploma from Universidad Tecnica Federico Santa Maria (Chile). He is doing his PhD on IoT for Smart Agriculture at IMS lab, University of Bordeaux. He is currently R&D Group Director and General Manager of Synopsys Chile. He has expertise and knowledge in business and technology and understands very well the trends of the electronic industry; therefore, he is often consulted for new technological business development. He has published several papers in IoT, EDA and embedded systems development, and since 2007 he has been invited to several Latin American Conferences (Argentina, Brazil, Chile, Mexico, Peru and Uruguay) to talk about Circuit Design, EDA, IoT, and Embedded Systems. Since 2012 he is chair of the IEEE Chilean chapter of the CASS. He is also the President of the Chilean Electronic and Electrical Industry Association (AIE). He has been part of several conferences TCP (ISCAS, ICECS, LASCAS) and is chairing the EDA and Circuit design Sub-Committee for ICECS. He is also Program Co-Chair of FoodCAS. Since 2018 he is Chair of LASCAS Steering Committee.
Alejandro Estay
Electronic Engineer from Universidad Catolica de Valparaiso (2019). Previous experience in electronic design for electronic warfare and RF. Working as Applications Engineer for Synopsys since 2022, for Formal Verification products. Digital Design Laboratory Instructor at Universidad Tecnica Federico Santa Maria since 2022 and contributing with teaching material since 2020.
Ariana Musello
Ariana Musello is an Electronic Engineer with a minor in Computer Science Engineering from Universidad San Francisco de Quito (USFQ), Ecuador. After graduating Summa Cum Laude in 2021 as Valedictorian, she began her career at Synopsys, Chile, as a Test & Validation Engineer in the Design Technology Group. She specializes in automation through creative scripting, infrastructure development to optimize processes, and testing of Synopsys’ EDA tools, with a deep understanding of the integrated circuit design flow. She previously worked as a Research Assistant at USFQ’s Instituto de Micro y Nanoelectrónica, focusing on spintronic devices, neural networks and circuit design with novel topologies, publishing five papers and participating in the design of Ecuador´s first VLSI microchip. She was also Chair of USF´s 2021 IEEE Student Branch and USFQ’s 2020 Women in Engineering Affinity Group. Ariana has a keen interest in artificial intelligence, computer architecture, and science communication, with a focus on exploring interdisciplinary approaches to the fields of electronics and programming. She is passionate about learning and teaching and, is committed to strengthening the presence of women in STEM.
Benjamín Villegas
Benjamín Villegas has a Master of Science (MSc.) in Electronic Engineering with a minor in Computers, from the Universidad Técnica Federico Santa María (UTFSM) in Valparaiso, Chile. He currently works as a product engineer (PE) at Synopsys since March 2024, supporting Power Analysis capabilities of Synthesis and Place & Route tools. While pursuing his master’s degree, he worked as a research assistant with a focus on microelectronic design, RISC-V and System on Chip (SoC) technology. He has also performed research in topics related to data science, machine learning (ML) and Internet of Things (IoT).
Esteban Viveros is an Electronic Engineer from Universidad de Concepción (Concepcion, Chile).
He started to work at Synopsys on December 2013 as Quality Engineer and now he is R&D Manager of a team in Chile Site.
The PV team is part of the Digital Design Group (DDG) and works on the “Product Validation” of the Synopsys tools used for RTL Synthesis, Test, Physical Implementation (Place and Route), Formal Verification and Sign-off. His team is responsible of the quality of the tools focusing on the stability, performance, usability and QoR (Quality of Results). The team interacts daily with colleagues and internal/external customers in different parts of the world (mainly US, China and Taiwan).
Besides that, Esteban actively collaborates on the university training activities dictated by Synopsys Chile.
José Martínez is an Electrical Engineer with mention in Electronics and Telecommunications, graduated from Universidad de Costa Rica. He holds a master’s degree in Management and Human Resources. José started working at Intel Costa Rica in 2014 where he held different roles such as Structural Designer, focusing on thermal analysis, Product Content Validation, centered in Array MBIST DFT, including the pre-silicon and post-silicon verification, repair methodology for redundant SRAMs, NPI (new product introduction), functional content writer for coverage increase, as well as OSNH (Operative System No-Harm) Engineer, in which he was directly involved in platform validation on different soft/hard reset states, performance, OS and uCode scalability, as well as part of the chip security reactive team. Since 2022 he works at Synopsys Chile. Currently, José is part of the CCSG team working towards PPA (power, performance, area) push; improving customers QoR results in a scalable and reproducible methodology.
Intel has been driving an aggressive acceleration in the integrated circuit fabrication
technologies, aiming to create 5 different nodes in 4 years (something never done before). This challenge is calling for a massive transformation of the whole IC design and fabrication process, from the design phase to the final assembly and test, proving Moore’s law is alive and well. On this talk, we intend to present an overview of this transformation and the relevance of updated skills and tools for the technical professionals in the different stages of the process of creating the world’s most advanced microchips.
Luis C. Rosales is an engineering manager at Intel in the product architecture and design group. Holds an Electronics Engineering degree and an MBA. Prior to Intel, Luis was part of an ASIC design and verification group dedicated to networking devices and various embedded system software design and verification. In his current role, Luis contributes to the Intel evo program, aiming to incorporate user experiences into the microprocessor design process.
Fernando Rivas Zuñiga holds an Electrical Engineering degree. Prior to intel, he worked as a university professor, but since 2020 he contributes as a Product Development Engineer in the Manufacturing and Product Engineering Group, where his current role is on delivering test capability in preparation for a product running at high volume manufacturing.
Functional verification of integrated circuits (ICs) is a vital process in IC design as it helps to ensure the correct operation of the designs. In this talk we will discuss the principles and concepts that govern the functional verification of ICs. We will also discuss the existing verification methodologies, verification tools and functional coverage of designs. Finally, we will talk about the challenges and opportunities of this niche in the Costa Rican labor market.
Carlos Salazar Garcia is an electronic engineer with a master’s degree in electronic engineering with emphasis in embedded systems and a PhD in engineering where he worked on the simulation of biologically accurate neural networks using FPGAs. Dr. Salazar has experience in both industry and academia strongly linked to the semiconductor industry, working on digital circuit design and test development for complex SoCs, and integration of complex nonlinear numerical model emulation in multi-FPGA systems using high-speed interfaces. He also has extensive experience in digital circuit design on FPGAs both at the RTL level and using high-level C++ synthesis. He is passionate about the advancement of technology.