Program

Time	Topic	Lecturer
8:30 – 9:00	Event Registration
From 9:00 to 17:30	Introduction to Digital Design Flow	Víctor Grimblatt
	Verilog for Synthesis	Víctor Grimblatt
	Lunch Break
	Fundamentals of CMOS I	Víctor Grimblatt
	Simulation of Digital Circuits with VCS	Víctor Grimblatt
17:30 – 18:30	Keynote	(TBD)

Time	Topic	Lecturer
From 9:00 to 17:30	Fundamentals of CMOS II	Víctor Grimblatt
	Lab 1: Verilog	Víctor Grimblatt
	Lunch Break
	Introduction to Fabrication of ICs	Víctor Grimblatt
	Lab 2: Verilog	Víctor Grimblatt
17:30 – 18:30	Keynote	(TBD)

Time	Topic	Lecturer
From 9:00 to 17:30	Design Compiler I	Juan Orellana
	Design Compiler II	Juan Orellana
	Lunch Break
	Lab 3: Synthesis with Design Compiler	Juan Orellana
	Lab 4: Synthesis with Design Compiler	Juan Orellana
17:30 – 18:30	Keynote	(TBD)

Time	Topic	Lecturer
From 9:00 to 17:30	IC Compiler I	Ronaldo Serrano
	IC Compiler II	Ronaldo Serrano
	Lunch Break
	Lab 5: Place & Route with IC Compiler	Ronaldo Serrano
	Lab 6: Place & Route with IC Compiler	Ronaldo Serrano
17:30 – 18:30	Keynote	(TBD)

Time	Topic	Lecturer
From 09:00 to 17:00	Lab 7: Final Review	(TBD)
	Evaluation
	Lunch Break
	TBD
	Event Closure