Program
| Time | Topic | Lecturer |
|---|---|---|
| Monday - 3/24/2025 | ||
| 8:30 - 9:00 | Event Registration | |
| 9:00 - 18:00 | Introduction to Digital Design Flow Verilog for Synthesis Lunch Break Fundamentals of CMOS I Simulation of Digital Circuits with VCS | Víctor Grimblatt |
| Tuesday - 3/25/2025 | ||
| 9:00 - 18:00 | Fundamentals of CMOS II Lab 1: Verilog Lunch Break Introduction to Fabrication of ICs Lab 2: Verilog | Víctor Grimblatt |
| Wednesday - 3/26/2025 | ||
| 9:00 - 18:00 | Design Compiler I Design Compiler II Lunch Break Lab 3: Synthesis with Design Compiler Lab 4: Synthesis with Design Compiler | Ariana Musello |
| Thursday - 3/27/2025 | ||
| 9:00 - 18:00 | IC Compiler I IC Compiler II Lunch Break Lab 5: Place & Route with IC Compiler Lab 6: Place & Route with IC Compiler | Jose Martínez |
| Friday - 3/28/2025 | ||
| 9:00 - 18:00 | Lab 7: Final Review Evaluation Lunch Break Event Closure | Ariana Musello, Jose Martínez |