Program
| Hora | Lunes - 24/3/25 | Martes - 25/3/25 | Miércoles - 26/3/25 | Jueves - 27/3/25 | Viernes - 28/3/25 |
|---|---|---|---|---|---|
| 08:30 | - | - | - | - | |
| 09:00 | Event registration Introduction to Digital Design Flow (Juan Romero) |
Fundamentals of CMOS (Ronald Valenzuela) |
Design Compiler I (Esteban Viveros) |
IC Compiler I (Ronald Valenzuela) |
Lab Final |
| 10:30 | Coffee break | ||||
| 11:00 | Verilog for Synthesis (Juan Romero) |
Simulation of Digital Circuits with VCS (Juan Romero) |
Design Compiler II (Esteban Viveros) |
IC Compiler II (Ronald Valenzuela) |
Lab Final |
| 12:30 | Lunch Break | ||||
| 14:00 | Lab 1 Verilog (Juan Romero) |
Lab 1/2: Verilog (Juan Romero) |
Lab 3: Synthesis with Design Compiler (Esteban Viveros) |
Lab 5: Place & Route with IC Compiler (Ronald Valenzuela) |
Evaluation and Closure |
| 15:30 | Coffee break | ||||
| 16:00 | Lab 1 Verilog (Juan Romero) |
Lab 2: Verilog (Juan Romero) |
Lab 4: Synthesis with Design Compiler (Esteban Viveros) |
Lab 6: Place & Route with IC Compiler (Ronald Valenzuela) |
|
| 17:30 | |||||