{"id":852,"date":"2025-04-04T19:00:22","date_gmt":"2025-04-04T19:00:22","guid":{"rendered":"https:\/\/asic-chile.cl\/vlsisoc\/?page_id=852"},"modified":"2025-07-17T14:21:43","modified_gmt":"2025-07-17T14:21:43","slug":"keynotes","status":"publish","type":"page","link":"https:\/\/asic-chile.cl\/vlsisoc\/keynotes\/","title":{"rendered":"Keynotes"},"content":{"rendered":"\t\t
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Keynotes<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Keynote – Cryogenic CMOS design techniques for scaled quantum computing systems<\/h3>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Abstract:<\/strong> This talk will cover practical challenges for cryogenic CMOS designs for next generation quantum computing. Starting from system level, it will detail the design considerations for a non-multiplexed, semi-autonomous, transmon qubit state controller (QSC) implemented in 14nm CMOS FinFET technology. The QSC includes an augmented general-purpose digital processor that supports waveform generation and phase rotation operations
combined with a low power current-mode single sideband upconversion I\/Q mixer-based RF arbitrary waveform generator (AWG). Implemented in 14nm CMOS FinFET technology, the
QSC generates control signals in its target 4.5GHz to 5.5 GHz frequency range, achieving an SFDR &gt; 50dB for a signal bandwidth of 500MHz. With the controller operating in the 4K stage of a cryostat and connected to a transmon qubit in the cryostat\u2019s millikelvin stage, measured transmon T1 and T2 coherence times were 75.7\u03bcs and 73\u03bcs, respectively, in each case comparable to results achieved using conventional room temperature controls. In further tests with transmons, a qubit-limited error rate of 7.76×10-4 per Clifford gate is achieved, again comparable to results achieved using room temperature controls. The QSC\u2019s maximum RF output power is -18 dBm, and power dissipation per qubit under active control is 23mW.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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Bio:<\/strong> Sudipto Chakraborty received his B. Tech from Indian Institute of Technology, Kharagpur in 1998 and Ph.D. in EE from Georgia Institute of Technology in 2002. He worked as a researcher in Georgia Electronic Design Center (GEDC) till 2004. Since 2004 to 2016, he was a senior member of technical staff at Texas Instruments where he contributed to low power integrated circuit design in more than 10 product families in the areas of automotive, wireless, medical and microcontrollers. Since 2017, he has been working at the IBM T. J. Watson Research Center where he leads the low power circuit design for next generation quantum computing applications using nano CMOS technology nodes. He has authored or co-authored more than 75 papers, two books and holds 76 US patents. He has served in the technical program committees of various conferences including CICC, RFIC, IMS and has been elected as an IBM master inventor in 2022 for his contributions.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Keynote – Multi-Die Design and Integration<\/h3>

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Abstract: <\/strong>The talk will cover the emerging technologies in advanced packaging and the challenges in Multi-die\/3D-IC Integration, and dive deep to design enablement, implementation methods, holistic analysis on bother electronics and thermal, and co-design and co-optimization. The talk will also address the new security and test issues in multi-die system.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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Bio: <\/strong>Brandon Wang is a Vice President of Technology Strategy at Office of the CEO at Synopsys. Brandon oversees corporate level technology roadmaps and strategies for growth, including global strategic and ecosystem partnerships, and M&A\/investments for new horizons. He also heads the Chief Innovation Office, championing organic innovations and worldwide academic and research partnerships. Prior to joining Synopsys in 2018, Brandon served executive and senior roles at Cadence, ARM, Qualcomm, and Lattice in chief strategy office, product marketing, and R&D organizations for over two decades. Brandon is currently serving at the board of Efabless corporation, and as a limited partner\/Investment Council member at Imec.Xpand, an affiliated VC to Imec. He is also a Limited Partner at AIX ventures, a leading venture capital firm focusing on AI investment and an LP and Technical Advisory Board Member at Black Opal ventures, who invests in life science and healthcare.\u00a0\u00a0An Electrical and Computer Engineer by training, Brandon holds 10 patents, and has published at 20+ IEEE conferences, in journal papers and invited talks in the areas of 3D-IC, Machine Learning, HW security, High-speed Interfaces, Low Power CPU, FPGA and Memory Designs. He is a chapter author of a recent book, \u201cDirect Copper Interconnection for Advanced Semiconductor Technology\u201d. He also has an MBA degree from the Wharton School at the University of Pennsylvania.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Keynote – Understanding the brain, from the perspective of EE<\/h3>

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Abstract: <\/strong>There are many important tasks where the brain outperforms our best existing technologies.\u00a0 <\/span>Understanding how the brain does these tasks will likely lead to commensurate performance improvements in our own technology.\u00a0 <\/span>But how to understand the brain?\u00a0 <\/span>The first part of this talk will summarize our current efforts in brain study, many using techniques borrowed from, and understandable to, EEs.\u00a0 <\/span>The second part of the talk will extend this analysis to aspects of the brain that are not yet well understood, again borrowing tools and techniques from electrical engineering.\u00a0 <\/span>The talk will end with some (hopefully informed) speculation on where this may lead.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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Bio: <\/strong>Lou Scheffer is an American EE and biologist.\u00a0 <\/span>He graduated from Caltech in EE and worked for several years at HP (now Keysight) designing test equipment.\u00a0 <\/span>Frustrated by the limited chip design tools of the time, he went as a grad student to Stanford, specializing in design automation.\u00a0 <\/span>He then worked in the industry (primarily Cadence) building chip design tools for almost 30 years.\u00a0 <\/span>While at a EE conference in the early 2000s, he attended a fascinating talk about what was then known about the wiring of a tiny brain (C. Elegans with 302 neurons).\u00a0 <\/span>This led to further interest, and in 2008 he joined the Howard Hughes Medical Institute, where he has been working on reconstructing, then understanding, the brains of larger and more complex animals.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Keynotes Sudipto Chakraborty IBM T. J. Watson Research Center Keynote – Cryogenic CMOS design techniques for scaled quantum computing systems Abstract: This talk will cover practical challenges for cryogenic CMOS designs for next generation quantum computing. Starting from system level, it will detail the design considerations for a non-multiplexed, semi-autonomous, transmon qubit state controller (QSC) […]<\/p>\n","protected":false},"author":2,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"elementor_header_footer","meta":{"_acf_changed":false,"footnotes":""},"class_list":["post-852","page","type-page","status-publish","hentry"],"acf":[],"yoast_head":"\nKeynotes - Vlsisisoc<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/asic-chile.cl\/vlsisoc\/keynotes\/\" \/>\n<meta property=\"og:locale\" content=\"es_ES\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Keynotes - Vlsisisoc\" \/>\n<meta property=\"og:description\" content=\"Keynotes Sudipto Chakraborty IBM T. J. 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