{"id":422,"date":"2025-01-06T01:04:16","date_gmt":"2025-01-06T01:04:16","guid":{"rendered":"https:\/\/asic-chile.cl\/vlsisoc\/?page_id=422"},"modified":"2025-06-04T13:38:24","modified_gmt":"2025-06-04T13:38:24","slug":"regular-papers","status":"publish","type":"page","link":"https:\/\/asic-chile.cl\/vlsisoc\/regular-papers\/","title":{"rendered":"Regular Papers"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-page\" data-elementor-id=\"422\" class=\"elementor elementor-422\">\n\t\t\t\t<div class=\"elementor-element elementor-element-446e39e e-flex e-con-boxed e-con e-parent\" data-id=\"446e39e\" data-element_type=\"container\" data-e-type=\"container\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t<div class=\"elementor-element elementor-element-ff5a49f e-con-full e-flex e-con e-child\" data-id=\"ff5a49f\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-9627485 e-con-full e-flex e-con e-child\" data-id=\"9627485\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t<div class=\"elementor-element elementor-element-1fd3f0e elementor-widget elementor-widget-spacer\" data-id=\"1fd3f0e\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-e618f0d elementor-widget elementor-widget-heading\" data-id=\"e618f0d\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">Regular Papers<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-f4f2901 e-con-full e-flex e-con e-child\" data-id=\"f4f2901\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-3327602 e-flex e-con-boxed e-con e-parent\" data-id=\"3327602\" data-element_type=\"container\" data-e-type=\"container\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-680642e elementor-widget elementor-widget-text-editor\" data-id=\"680642e\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p>Download the complete\u00a0pdf version\u00a0of the\u00a0call for papers here.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-1967259 elementor-align-center elementor-widget elementor-widget-button\" data-id=\"1967259\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"button.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<div class=\"elementor-button-wrapper\">\n\t\t\t\t\t<a class=\"elementor-button elementor-button-link elementor-size-sm\" href=\"http:\/\/asic-chile.cl\/wp-content\/uploads\/sites\/21\/2025\/06\/VLSISoC2025CFPV10.pdf\" target=\"_blank\">\n\t\t\t\t\t\t<span class=\"elementor-button-content-wrapper\">\n\t\t\t\t\t\t\t\t\t<span class=\"elementor-button-text\">Download here<\/span>\n\t\t\t\t\t<\/span>\n\t\t\t\t\t<\/a>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-f4e35f8 e-flex e-con-boxed e-con e-parent\" data-id=\"f4e35f8\" data-element_type=\"container\" data-e-type=\"container\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-ef3672d elementor-widget elementor-widget-spacer\" data-id=\"ef3672d\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-77712427 e-flex e-con-boxed e-con e-parent\" data-id=\"77712427\" data-element_type=\"container\" data-e-type=\"container\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-b18211c elementor-widget elementor-widget-heading\" data-id=\"b18211c\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">Guidelines<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-5ecab0a elementor-widget elementor-widget-text-editor\" data-id=\"5ecab0a\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p>Each submitted paper should be a complete PDF manuscript, up to four (4) pages (inclusive of all figures, tables, and bibliography) in a standard IEEE format: A4 pages, two columns, single spaced, 10 points Times New Roman font. IEEE template that can be found [here]. Papers not compliant with the IEEE template or exceeding the page limit will be returned without review! Papers identified as double submissions with respect to other conferences and\/or journals will be rejected.<\/p><p>A submission of a scientific paper is considered as a commitment that, upon acceptance, authors will submit their camera-ready version for inclusion in the formal proceedings and will present the paper (or the poster) at the symposium. VLSI-SoC reserves the right to remove from IEEE Xplore papers and posters that have not been presented at the symposium.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-a1e6892 e-grid e-con-boxed e-con e-parent\" data-id=\"a1e6892\" data-element_type=\"container\" data-e-type=\"container\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-4b41fdd elementor-widget elementor-widget-spacer\" data-id=\"4b41fdd\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-af173e8 elementor-widget elementor-widget-heading\" data-id=\"af173e8\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">Topic Areas for Submission<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-1313382 e-grid e-con-boxed e-con e-parent\" data-id=\"1313382\" data-element_type=\"container\" data-e-type=\"container\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-65607dc elementor-widget elementor-widget-text-editor\" data-id=\"65607dc\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p>Topics of interest include but are not limited to:<\/p><ul><li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"8\" data-list-defn-props=\"{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"1\" data-aria-level=\"1\">Analog and Mixed-Signal IC Design<\/li><li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"8\" data-list-defn-props=\"{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"1\" data-aria-level=\"1\">3-D Integration<\/li><li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"8\" data-list-defn-props=\"{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"1\" data-aria-level=\"1\">Physical Design<\/li><li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"8\" data-list-defn-props=\"{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"1\" data-aria-level=\"1\">\u00a0Electronic Design Automation<\/li><li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"8\" data-list-defn-props=\"{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"1\" data-aria-level=\"1\">Variability, Reliability, Fault Tolerance and Test<\/li><li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"8\" data-list-defn-props=\"{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"1\" data-aria-level=\"1\">\u00a0Digital Signal Processing and Image Processing SoC Design<\/li><li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"8\" data-list-defn-props=\"{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"1\" data-aria-level=\"1\">Prototyping, Validation, Verification, Modelling, and Simulation<\/li><\/ul>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-9c2451d elementor-widget elementor-widget-text-editor\" data-id=\"9c2451d\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<ul><li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"8\" data-list-defn-props=\"{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"1\" data-aria-level=\"1\">Embedded Systems and Processors, Hardware\/Software Codesign<\/li><li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"8\" data-list-defn-props=\"{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"1\" data-aria-level=\"1\">Processor Architectures and Multicore SOCs<\/li><li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"8\" data-list-defn-props=\"{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"1\" data-aria-level=\"1\">Logic and High-Level Synthesis<\/li><li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"8\" data-list-defn-props=\"{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"1\" data-aria-level=\"1\">Low-Power and Thermal-aware Design<\/li><li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"8\" data-list-defn-props=\"{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"1\" data-aria-level=\"1\">Reconfigurable SoC Systems for Energy and Reliability<\/li><li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"8\" data-list-defn-props=\"{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"1\" data-aria-level=\"1\">Green Computing Systems<\/li><li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"8\" data-list-defn-props=\"{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"1\" data-aria-level=\"1\">Circuits and Systems for Micro-sensing Applications<\/li><\/ul>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-9daae37 e-flex e-con-boxed e-con e-parent\" data-id=\"9daae37\" data-element_type=\"container\" data-e-type=\"container\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-fe93c30 elementor-widget elementor-widget-spacer\" data-id=\"fe93c30\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-934b6cb e-flex e-con-boxed e-con e-parent\" data-id=\"934b6cb\" data-element_type=\"container\" data-e-type=\"container\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-cf4db2b elementor-widget elementor-widget-image\" data-id=\"cf4db2b\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<img fetchpriority=\"high\" decoding=\"async\" width=\"800\" height=\"194\" src=\"https:\/\/asic-chile.cl\/vlsisoc\/wp-content\/uploads\/sites\/21\/2025\/01\/fondo-1024x248.png\" class=\"attachment-large size-large wp-image-553\" alt=\"\" srcset=\"https:\/\/asic-chile.cl\/vlsisoc\/wp-content\/uploads\/sites\/21\/2025\/01\/fondo-1024x248.png 1024w, https:\/\/asic-chile.cl\/vlsisoc\/wp-content\/uploads\/sites\/21\/2025\/01\/fondo-300x73.png 300w, https:\/\/asic-chile.cl\/vlsisoc\/wp-content\/uploads\/sites\/21\/2025\/01\/fondo-768x186.png 768w, https:\/\/asic-chile.cl\/vlsisoc\/wp-content\/uploads\/sites\/21\/2025\/01\/fondo-1536x371.png 1536w, https:\/\/asic-chile.cl\/vlsisoc\/wp-content\/uploads\/sites\/21\/2025\/01\/fondo-2048x495.png 2048w\" sizes=\"(max-width: 800px) 100vw, 800px\" \/>\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-6cd449a e-flex e-con-boxed e-con e-parent\" data-id=\"6cd449a\" data-element_type=\"container\" data-e-type=\"container\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-1a2e640 elementor-widget elementor-widget-spacer\" data-id=\"1a2e640\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-09bd172 e-flex e-con-boxed e-con e-parent\" data-id=\"09bd172\" data-element_type=\"container\" data-e-type=\"container\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-a74ae6e e-flex e-con-boxed e-con e-parent\" data-id=\"a74ae6e\" data-element_type=\"container\" data-e-type=\"container\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t<div class=\"elementor-element elementor-element-0c7a902 e-con-full e-flex e-con e-child\" data-id=\"0c7a902\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t<div class=\"elementor-element elementor-element-97b4d57 elementor-widget elementor-widget-heading\" data-id=\"97b4d57\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">Publications<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-8739560 elementor-widget elementor-widget-text-editor\" data-id=\"8739560\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p>VLSI-SoC\u201925 will produce electronic formal proceedings &#8211; with ISBN, and to be indexed in the IEEE Xplore<br \/>digital library and other bibliographical search engines. Scientific papers can be accepted for:<\/p><ul><li>oral presentation: you will be asked to prepare a final \u00a0a final 4 pages + a 5th page with only references manuscript for inclusion in the formal<br \/>proceedings.<\/li><li>poster presentation: in this case, a 4-page paper will be included in the formal proceedings.<br \/>The formal proceedings will contain the PDF files of all accepted papers of accepted posters.\u00a0<br \/>The Best Paper Award of VLSI-SoC\u201925 will be presented at VLSI-SoC\u201926.<\/li><\/ul>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-f9036c3 e-con-full e-flex e-con e-child\" data-id=\"f9036c3\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t<div class=\"elementor-element elementor-element-7e98289 elementor-widget elementor-widget-heading\" data-id=\"7e98289\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">Book by Springer<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-140cb7f elementor-widget elementor-widget-text-editor\" data-id=\"140cb7f\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p>A selection of extended version best regular accepted papers at the conference will be selected for publication in a book by Springer. The details information will be sent to the authors timely.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-097cf8e e-flex e-con-boxed e-con e-parent\" data-id=\"097cf8e\" data-element_type=\"container\" data-e-type=\"container\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-56cd056 elementor-widget elementor-widget-spacer\" data-id=\"56cd056\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-b7f36e9 e-flex e-con-boxed e-con e-parent\" data-id=\"b7f36e9\" data-element_type=\"container\" data-e-type=\"container\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-f4523e7 elementor-widget elementor-widget-spacer\" data-id=\"f4523e7\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-f12c342 e-grid e-con-boxed e-con e-parent\" data-id=\"f12c342\" data-element_type=\"container\" data-e-type=\"container\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-09da1f1 elementor-widget elementor-widget-heading\" data-id=\"09da1f1\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<h3 class=\"elementor-heading-title elementor-size-default\">Contact Information<\/h3>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-029301f elementor-widget elementor-widget-text-editor\" data-id=\"029301f\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p class=\"p1\">For more information, please<\/p><p class=\"p1\">contact the Program Chair<\/p><p class=\"p1\">Ricardo Reis <a href=\"mailto:reis@inf.ufrgs.br\">reis@inf.ufrgs.br<\/a><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-f66909f elementor-widget elementor-widget-text-editor\" data-id=\"f66909f\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p class=\"p1\">or Patrick Groeneveld<\/p><p class=\"p1\"><br \/><a href=\"mailto:patrickgroeneveld1@gmail.com\">patrickgroeneveld1@gmail.com<\/a><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-62da419 e-flex e-con-boxed e-con e-parent\" data-id=\"62da419\" data-element_type=\"container\" data-e-type=\"container\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-cfd935a elementor-widget elementor-widget-spacer\" data-id=\"cfd935a\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>Regular Papers Download the complete\u00a0pdf version\u00a0of the\u00a0call for papers here. Download here Guidelines Each submitted paper should be a complete PDF manuscript, up to four (4) pages (inclusive of all figures, tables, and bibliography) in a standard IEEE format: A4 pages, two columns, single spaced, 10 points Times New Roman font. IEEE template that can [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"elementor_header_footer","meta":{"_acf_changed":false,"footnotes":""},"class_list":["post-422","page","type-page","status-publish","hentry"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.1.1 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Regular Papers - Vlsisisoc<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/asic-chile.cl\/vlsisoc\/regular-papers\/\" \/>\n<meta property=\"og:locale\" content=\"es_ES\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Regular Papers - Vlsisisoc\" \/>\n<meta property=\"og:description\" content=\"Regular Papers Download the complete\u00a0pdf version\u00a0of the\u00a0call for papers here. Download here Guidelines Each submitted paper should be a complete PDF manuscript, up to four (4) pages (inclusive of all figures, tables, and bibliography) in a standard IEEE format: A4 pages, two columns, single spaced, 10 points Times New Roman font. IEEE template that can [&hellip;]\" \/>\n<meta property=\"og:url\" content=\"https:\/\/asic-chile.cl\/vlsisoc\/regular-papers\/\" \/>\n<meta property=\"og:site_name\" content=\"Vlsisisoc\" \/>\n<meta property=\"article:modified_time\" content=\"2025-06-04T13:38:24+00:00\" \/>\n<meta property=\"og:image\" content=\"http:\/\/asic-chile.cl\/wp-content\/uploads\/sites\/21\/2025\/01\/fondo-1024x248.png\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Tiempo de lectura\" \/>\n\t<meta name=\"twitter:data1\" content=\"2 minutos\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"WebPage\",\"@id\":\"https:\/\/asic-chile.cl\/vlsisoc\/regular-papers\/\",\"url\":\"https:\/\/asic-chile.cl\/vlsisoc\/regular-papers\/\",\"name\":\"Regular Papers - Vlsisisoc\",\"isPartOf\":{\"@id\":\"https:\/\/asic-chile.cl\/vlsisoc\/#website\"},\"primaryImageOfPage\":{\"@id\":\"https:\/\/asic-chile.cl\/vlsisoc\/regular-papers\/#primaryimage\"},\"image\":{\"@id\":\"https:\/\/asic-chile.cl\/vlsisoc\/regular-papers\/#primaryimage\"},\"thumbnailUrl\":\"http:\/\/asic-chile.cl\/wp-content\/uploads\/sites\/21\/2025\/01\/fondo-1024x248.png\",\"datePublished\":\"2025-01-06T01:04:16+00:00\",\"dateModified\":\"2025-06-04T13:38:24+00:00\",\"breadcrumb\":{\"@id\":\"https:\/\/asic-chile.cl\/vlsisoc\/regular-papers\/#breadcrumb\"},\"inLanguage\":\"es\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\/\/asic-chile.cl\/vlsisoc\/regular-papers\/\"]}]},{\"@type\":\"ImageObject\",\"inLanguage\":\"es\",\"@id\":\"https:\/\/asic-chile.cl\/vlsisoc\/regular-papers\/#primaryimage\",\"url\":\"http:\/\/asic-chile.cl\/wp-content\/uploads\/sites\/21\/2025\/01\/fondo-1024x248.png\",\"contentUrl\":\"http:\/\/asic-chile.cl\/wp-content\/uploads\/sites\/21\/2025\/01\/fondo-1024x248.png\"},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\/\/asic-chile.cl\/vlsisoc\/regular-papers\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Portada\",\"item\":\"https:\/\/asic-chile.cl\/vlsisoc\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"Regular Papers\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\/\/asic-chile.cl\/vlsisoc\/#website\",\"url\":\"https:\/\/asic-chile.cl\/vlsisoc\/\",\"name\":\"Vlsisisoc\",\"description\":\"\",\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\/\/asic-chile.cl\/vlsisoc\/?s={search_term_string}\"},\"query-input\":{\"@type\":\"PropertyValueSpecification\",\"valueRequired\":true,\"valueName\":\"search_term_string\"}}],\"inLanguage\":\"es\"}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"Regular Papers - Vlsisisoc","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/asic-chile.cl\/vlsisoc\/regular-papers\/","og_locale":"es_ES","og_type":"article","og_title":"Regular Papers - Vlsisisoc","og_description":"Regular Papers Download the complete\u00a0pdf version\u00a0of the\u00a0call for papers here. Download here Guidelines Each submitted paper should be a complete PDF manuscript, up to four (4) pages (inclusive of all figures, tables, and bibliography) in a standard IEEE format: A4 pages, two columns, single spaced, 10 points Times New Roman font. IEEE template that can [&hellip;]","og_url":"https:\/\/asic-chile.cl\/vlsisoc\/regular-papers\/","og_site_name":"Vlsisisoc","article_modified_time":"2025-06-04T13:38:24+00:00","og_image":[{"url":"http:\/\/asic-chile.cl\/wp-content\/uploads\/sites\/21\/2025\/01\/fondo-1024x248.png","type":"","width":"","height":""}],"twitter_card":"summary_large_image","twitter_misc":{"Tiempo de lectura":"2 minutos"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"WebPage","@id":"https:\/\/asic-chile.cl\/vlsisoc\/regular-papers\/","url":"https:\/\/asic-chile.cl\/vlsisoc\/regular-papers\/","name":"Regular Papers - Vlsisisoc","isPartOf":{"@id":"https:\/\/asic-chile.cl\/vlsisoc\/#website"},"primaryImageOfPage":{"@id":"https:\/\/asic-chile.cl\/vlsisoc\/regular-papers\/#primaryimage"},"image":{"@id":"https:\/\/asic-chile.cl\/vlsisoc\/regular-papers\/#primaryimage"},"thumbnailUrl":"http:\/\/asic-chile.cl\/wp-content\/uploads\/sites\/21\/2025\/01\/fondo-1024x248.png","datePublished":"2025-01-06T01:04:16+00:00","dateModified":"2025-06-04T13:38:24+00:00","breadcrumb":{"@id":"https:\/\/asic-chile.cl\/vlsisoc\/regular-papers\/#breadcrumb"},"inLanguage":"es","potentialAction":[{"@type":"ReadAction","target":["https:\/\/asic-chile.cl\/vlsisoc\/regular-papers\/"]}]},{"@type":"ImageObject","inLanguage":"es","@id":"https:\/\/asic-chile.cl\/vlsisoc\/regular-papers\/#primaryimage","url":"http:\/\/asic-chile.cl\/wp-content\/uploads\/sites\/21\/2025\/01\/fondo-1024x248.png","contentUrl":"http:\/\/asic-chile.cl\/wp-content\/uploads\/sites\/21\/2025\/01\/fondo-1024x248.png"},{"@type":"BreadcrumbList","@id":"https:\/\/asic-chile.cl\/vlsisoc\/regular-papers\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Portada","item":"https:\/\/asic-chile.cl\/vlsisoc\/"},{"@type":"ListItem","position":2,"name":"Regular Papers"}]},{"@type":"WebSite","@id":"https:\/\/asic-chile.cl\/vlsisoc\/#website","url":"https:\/\/asic-chile.cl\/vlsisoc\/","name":"Vlsisisoc","description":"","potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/asic-chile.cl\/vlsisoc\/?s={search_term_string}"},"query-input":{"@type":"PropertyValueSpecification","valueRequired":true,"valueName":"search_term_string"}}],"inLanguage":"es"}]}},"_links":{"self":[{"href":"https:\/\/asic-chile.cl\/vlsisoc\/wp-json\/wp\/v2\/pages\/422","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/asic-chile.cl\/vlsisoc\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/asic-chile.cl\/vlsisoc\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/asic-chile.cl\/vlsisoc\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/asic-chile.cl\/vlsisoc\/wp-json\/wp\/v2\/comments?post=422"}],"version-history":[{"count":0,"href":"https:\/\/asic-chile.cl\/vlsisoc\/wp-json\/wp\/v2\/pages\/422\/revisions"}],"wp:attachment":[{"href":"https:\/\/asic-chile.cl\/vlsisoc\/wp-json\/wp\/v2\/media?parent=422"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}