{"id":1114,"date":"2025-06-26T01:45:51","date_gmt":"2025-06-26T01:45:51","guid":{"rendered":"https:\/\/asic-chile.cl\/vlsisoc\/?page_id=1114"},"modified":"2025-07-14T16:45:31","modified_gmt":"2025-07-14T16:45:31","slug":"tutorials","status":"publish","type":"page","link":"https:\/\/asic-chile.cl\/vlsisoc\/tutorials\/","title":{"rendered":"Tutorials"},"content":{"rendered":"\t\t
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Tutorials<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t
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\n\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\tTutorial 1<\/span>\n\t\t\t\t\t<\/span>\n\t\t\t\t\t<\/a>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Tutorial 1 – Power Analysis &amp; Optimizations: Fundamentals to Advance
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Ronald Valenzuela and Benjam\u00edn Villegas \u2013 Synopsys (Chile)<\/h6>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Abstract:<\/strong>
Power efficiency is a critical design goal in modern SoC development. This tutorial is structured around three key pillars: Digital Design Flow, Power Analysis, and Power Optimizations. We
begin by presenting the overall SoC implementation flow, covering the key stages from RTL design to synthesis, floor-planning, place &amp; route, and signoff; with a hierarchical implementation perspective. Throughout this section, we highlight how power-related aspects are embedded within the broader design process, including considerations for common design
goals.
The second part focuses on the fundamentals of power analysis, including switching activity, dynamic and static components, and Liberty power models. We examine how EDA tools leverage this data for accurate estimation and reporting across the flow. The final section addresses power optimization and multi-voltage implementation techniques\u2014ranging from widely-used strategies such as clock gating and multi-VT optimization to more advanced methodologies like UPF-modeled voltage domains, level shifters, and isolation-aware synthesis.<\/p>

Outline:<\/strong><\/p>

  • Digital design flow<\/li>
  • Power analysis<\/li>
  • Power optimization<\/li><\/ul>

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    Tutorial 2 \u2013 Integrated circuits design using IHP SG13G2 open-source PDK exploring local and cloud-based design environments<\/h3>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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    Juan Sebastian Moya-Baquero (Symbiotic EDA, Colombia), Jorge Marin (AC3E\/USM, Chile), and Krzysztof Herman (IHP, Germany).<\/h6>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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    Abstract:<\/strong><\/p>

    The first part of this workshop will introduce IHP\u2019s open-source SG13G2 Process Design Kit (PDK). This PDK was developed to support innovative and accessible integrated circuit design for academic institutions and small-scale industries. The training covers two distinct design flows, analog and RF, and highlights the key aspects, tools, and methodologies involved in each.
    Participants will gain insight into the PDK’s core capabilities, explore design methodologies, and experience the synergy of powerful EDA tools. We will also explain the submission and participation process, offering attendees the opportunity to fabricate their own designs free of charge.<\/p>

    The second part of the workshop presents a chip design environment that provides cloud-based tools, preconfigured libraries, and support services to enhance the learning experience. The platform is designed to benefit a wide range of users, from students to researchers, by providing a Git-based environment that emphasizes control, ease of use, and collaboration. It simplifies handling coursework, enabling users to work effectively. This section of the tutorial will provide a comprehensive overview of the environment’s structure and integrated design and simulation tools. Then, attendees will gain practical design experience with open-source tools and workflows through a hands-on approach (only personal laptop required, access to tools will be via server).<\/p>

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    Outline:<\/strong><\/p>

    • Introduction to the IHP technology, PDK and open-source ecosystem<\/li>
    • Analog\/RF design flows<\/li>
    • An easy-to-use chip design environment that leverages git, a mature open-source node
      and open-source EDA tools for enhanced learning.<\/li><\/ul>

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      Tutorials Tutorial 1 Tutorial 2 Tutorial 1 – Power Analysis &amp; Optimizations: Fundamentals to AdvanceImplementations Ronald Valenzuela and Benjam\u00edn Villegas \u2013 Synopsys (Chile) Abstract:Power efficiency is a critical design goal in modern SoC development. This tutorial is structured around three key pillars: Digital Design Flow, Power Analysis, and Power Optimizations. Webegin by presenting the overall […]<\/p>\n","protected":false},"author":2,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"elementor_header_footer","meta":{"_acf_changed":false,"footnotes":""},"class_list":["post-1114","page","type-page","status-publish","hentry"],"acf":[],"yoast_head":"\nTutorials - Vlsisisoc<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/asic-chile.cl\/vlsisoc\/tutorials\/\" \/>\n<meta property=\"og:locale\" content=\"es_ES\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Tutorials - Vlsisisoc\" \/>\n<meta property=\"og:description\" content=\"Tutorials Tutorial 1 Tutorial 2 Tutorial 1 – Power Analysis &amp; Optimizations: Fundamentals to AdvanceImplementations Ronald Valenzuela and Benjam\u00edn Villegas \u2013 Synopsys (Chile) Abstract:Power efficiency is a critical design goal in modern SoC development. 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