{"id":493,"date":"2022-11-04T19:29:58","date_gmt":"2022-11-04T19:29:58","guid":{"rendered":"https:\/\/asic-chile.cl\/ucr\/?page_id=493"},"modified":"2025-12-16T14:41:42","modified_gmt":"2025-12-16T14:41:42","slug":"lecturers","status":"publish","type":"page","link":"https:\/\/asic-chile.cl\/ucr\/lecturers\/","title":{"rendered":"Lecturers"},"content":{"rendered":"\t\t
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Lecturers<\/h1>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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July 28 th – August 1 st , 2025<\/strong>
Every day from 9 am to 7 pm
Laboratorio de computadoras 111,
Facultad de Ingenier\u00eda,
Ciudad de la Investigaci\u00f3n,
Universidad de Costa Rica<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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Ariana Musello<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t
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Ariana Musello is an Electronic Engineer with a minor in Computer Science Engineering from Universidad San Francisco de Quito (USFQ), Ecuador. After graduating Summa Cum Laude in 2021 as Valedictorian, she began her career at Synopsys, Chile, as a Test & Validation Engineer in the Design Technology Group. She specializes in automation through creative scripting, infrastructure development to optimize processes, and testing of Synopsys\u2019 EDA tools, with a deep understanding of the integrated circuit design flow. She previously worked as a Research Assistant at USFQ\u2019s Instituto de Micro y Nanoelectr\u00f3nica, focusing on spintronic devices, neural networks and circuit design with novel topologies, publishing five papers and participating in the design of Ecuador\u00b4s first VLSI microchip. She was also Chair of USF\u00b4s 2021 IEEE Student Branch and USFQ\u2019s 2020 Women in Engineering Affinity Group. Ariana has a keen interest in artificial intelligence, computer architecture, and science communication, with a focus on exploring interdisciplinary approaches to the fields of electronics and programming. She is passionate about learning and teaching and, is committed to strengthening the presence of women in STEM.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Juan Romero<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t
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Juan Romero is an Electronic Engineer from the Industrial University of Santander-UIS (Bucaramanga, Colombia) with a master\u00b4s degree in electronic engineering from the same educational institution. Juan started working as a professor, and then jumped to work with Synopsys to be part of the Customer Success Group (CSG) around +2 years ago. He is the Verification Team Lead at CCSG, with background RTL, SoC network communication and functional verification.<\/p>

At Synopsys, Juan has been involved in helping the client when they have a problem related to the VCS and Verdi tools, both tools used during the functional verification process. The tasks he commonly faces are, providing information about the tools when required, ensuring that the problems that the client detects related to VCS and Verdi are resolved, helping during the process of migrating the design to a new version of the tool, and improving the performance at runtime and build time in the verification flow stage.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Jos\u00e9 Mart\u00ednez<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t
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Jos\u00e9 Mart\u00ednez is an Electrical Engineer with mention in Electronics and Telecommunications, graduated from Universidad de Costa Rica. He holds a master\u2019s degree in Management and Human Resources. Jos\u00e9 started working at Intel Costa Rica in 2014 where he held different roles such as Structural Designer, focusing on thermal analysis, Product Content Validation, centered in Array MBIST DFT, including the pre-silicon and post-silicon verification, repair methodology for redundant SRAMs, NPI (new product introduction), functional content writer for coverage increase, as well as OSNH (Operative System No-Harm) Engineer, in which he was directly involved in platform validation on different soft\/hard reset states, performance, OS and uCode scalability, as well as part of the chip security reactive team. Since 2022 he works at Synopsys Chile. Currently, Jos\u00e9 is part of the CCSG team working towards PPA (power, performance, area) push; improving customers QoR results in a scalable and reproducible methodology.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Lecturers July 28 th – August 1 st , 2025Every day from 9 am to 7 pmLaboratorio de computadoras 111, Facultad de Ingenier\u00eda,Ciudad de la Investigaci\u00f3n, Universidad de Costa Rica Ariana Musello Ariana Musello is an Electronic Engineer with a minor in Computer Science Engineering from Universidad San Francisco de Quito (USFQ), Ecuador. After graduating […]<\/p>\n","protected":false},"author":2,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"elementor_header_footer","meta":{"_acf_changed":false,"footnotes":""},"class_list":["post-493","page","type-page","status-publish","hentry"],"acf":[],"yoast_head":"\nLecturers - Digital Integrated Circuits Design Bootcamp San Jose, Costa Rica<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/asic-chile.cl\/ucr\/lecturers\/\" \/>\n<meta property=\"og:locale\" content=\"es_ES\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Lecturers - Digital Integrated Circuits Design Bootcamp San Jose, Costa Rica\" \/>\n<meta property=\"og:description\" content=\"Lecturers July 28 th – August 1 st , 2025Every day from 9 am to 7 pmLaboratorio de computadoras 111, Facultad de Ingenier\u00eda,Ciudad de la Investigaci\u00f3n, Universidad de Costa Rica Ariana Musello Ariana Musello is an Electronic Engineer with a minor in Computer Science Engineering from Universidad San Francisco de Quito (USFQ), Ecuador. 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