Program
| Hora | Lunes - 28/7/25 | Martes - 29/7/25 | Miércoles - 30/7/25 | Jueves - 31/7/25 | Viernes - 1/8/25 |
|---|---|---|---|---|---|
| 08:30 | Event Registration Intro to Digital Design Flow (Juan Romero) | - | - | - | - |
| 09:00 | Verilog for Synthesis (Juan Romero) |
Fundamentals of CMOS II (Juan Romero) |
Design Compiler I (Ariana Musello) |
IC Compiler I (José Martínez) |
Lab 7: Final Review (TBD) |
| 10:30 | Coffee break | ||||
| 11:00 | Fundamentals of CMOS I (Juan Romero) |
Lab 1: Verilog (Juan Romero) |
Design Compiler II (Ariana Musello) |
IC Compiler II (José Martínez) |
Evaluation |
| 12:30 | Lunch Break | ||||
| 14:00 | Simulation of Digital Circuits with VCS (Juan Romero) |
Introduction to Fabrication of ICs (Juan Romero) |
Lab 3: Synthesis with Design Compiler (Ariana Musello) |
Lab 5: Place & Route with IC Compiler (José Martínez) |
TBD |
| 15:30 | Coffee break | ||||
| 16:00 | - | Lab 2: Verilog (Juan Romero) |
Lab 4: Synthesis with Design Compiler (Ariana Musello) |
Lab 6: Place & Route with IC Compiler (José Martínez) |
Event Closure |
| 18:00 | Keynote (TBD) | Keynote (TBD) | Keynote (TBD) | Keynote (TBD) | - |