Victor Grimblatt has an engineering diploma in microelectronics from Institut Nationale Polytechnique de Grenoble (INPG – France) and an electronic engineering diploma from Universidad Tecnica Federico Santa Maria (Chile). He is doing his PhD on IoT for Smart Agriculture at IMS lab, University of Bordeaux. He is currently R&D Group Director and General Manager of Synopsys Chile. He has expertise and knowledge in business and technology and understands very well the trends of the electronic industry; therefore, he is often consulted for new technological business development. He has published several papers in IoT, EDA and embedded systems development, and since 2007 he has been invited to several Latin American Conferences (Argentina, Brazil, Chile, Mexico, Peru and Uruguay) to talk about Circuit Design, EDA, IoT, and Embedded Systems. Since 2012 he is chair of the IEEE Chilean chapter of the CASS. He is also the President of the Chilean Electronic and Electrical Industry Association (AIE). He has been part of several conferences TCP (ISCAS, ICECS, LASCAS) and is chairing the EDA and Circuit design Sub-Committee for ICECS. He is also is Program Co-Chair of FoodCAS. Since 2018 he is Chair of LASCAS Steering Committee.
Ronald Valenzuela currently manages a team of Product Engineers (PE) at Synopsys. With his team, they provide support on Power Optimization and Power Analysis capabilities of Synthesis and Place & Route tools. As PEs, they engage with customers to enable methodologies and also contribute to planning and testing of the tools. Ronald has 10 years of experience in EDA Industry, he is Electronics Engineer of Universidad de Concepción and has a certification on Integrated Circuit design from Stanford University, CA.
Esteban Viveros is an Electronic Engineer from Universidad de Concepción (Concepcion, Chile). He started to work at Synopsys on December 2013 as Quality Engineer and now he is R&D Manager of a team in Chile Site. The PV team is part of the Digital Design Group (DDG) and works on the "Product Validation" of the Synopsys tools used for RTL Synthesis, Test, Physical Implementation (Place and Route), Formal Verification and Sign-off. His team is responsible of the quality of the tools focusing on the stability, performance, usability and QoR (Quality of Results). The team interacts daily with colleagues and internal/external customers in different parts of the world (mainly US, China and Taiwan). Besides that, Esteban actively collaborates on the university training activities dictated by Synopsys Chile.