{"id":493,"date":"2022-11-04T19:29:58","date_gmt":"2022-11-04T19:29:58","guid":{"rendered":"https:\/\/asic-chile.cl\/inaoe\/?page_id=493"},"modified":"2025-12-16T15:11:55","modified_gmt":"2025-12-16T15:11:55","slug":"lecturers","status":"publish","type":"page","link":"https:\/\/asic-chile.cl\/inaoe\/lecturers\/","title":{"rendered":"Lecturers"},"content":{"rendered":"\t\t
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Lecturers<\/h1>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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March 24 th – March 28 th , 2025
Every day from 9 am to 6 pm
INAOE, Puebla, M\u00e9xico<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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Victor Grimblatt<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t
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Victor Grimblatt has an engineering diploma in microelectronics from Institut Nationale Polytechnique de Grenoble (INPG \u2013 France) and an electronic engineering diploma from Universidad Tecnica Federico Santa Maria (Chile). He is doing his PhD on IoT for Smart Agriculture at IMS lab, University of Bordeaux. He is currently R&D Group Director and General Manager of Synopsys Chile. He has expertise and knowledge in business and technology and understands very well the trends of the electronic industry; therefore, he is often consulted for new technological business development. He has published several papers in IoT, EDA and embedded systems development, and since 2007 he has been invited to several Latin American Conferences (Argentina, Brazil, Chile, Mexico, Peru and Uruguay) to talk about Circuit Design, EDA, IoT, and Embedded Systems. Since 2012 he is chair of the IEEE Chilean chapter of the CASS. He is also the President of the Chilean Electronic and Electrical Industry Association (AIE). He has been part of several conferences TCP (ISCAS, ICECS, LASCAS) and is chairing the EDA and Circuit design Sub-Committee for ICECS. He is also Program Co-Chair of FoodCAS. Since 2018 he is Chair of LASCAS Steering Committee.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Jos\u00e9 Mart\u00ednez<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t
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Jos\u00e9 Mart\u00ednez is an Electrical Engineer with mention in Electronics and Telecommunications, graduated from Universidad de Costa Rica. He holds a master\u2019s degree in Management and Human Resources. Jos\u00e9 started working at Intel Costa Rica in 2014 where he held different roles such as Structural Designer, focusing on thermal analysis, Product Content Validation, centered in Array MBIST DFT, including the pre-silicon and post-silicon verification, repair methodology for redundant SRAMs, NPI (new product introduction), functional content writer for coverage increase, as well as OSNH (Operative System No-Harm) Engineer, in which he was directly involved in platform validation on different soft\/hard reset states, performance, OS and uCode scalability, as well as part of the chip security reactive team. Since 2022 he works at Synopsys Chile. Currently, Jos\u00e9 is part of the CCSG team working towards PPA (power, performance, area) push; improving customers QoR results in a scalable and reproducible methodology.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Ariana Musello<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t
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Ariana Musello is an Electronic Engineer with a minor in Computer Science Engineering from Universidad San Francisco de Quito (USFQ), Ecuador. After graduating Summa Cum Laude in 2021 as Valedictorian, she began her career at Synopsys, Chile, as a Test & Validation Engineer in the Design Technology Group. She specializes in automation through creative scripting, infrastructure development to optimize processes, and testing of Synopsys\u2019 EDA tools, with a deep understanding of the integrated circuit design flow. She previously worked as a Research Assistant at USFQ\u2019s Instituto de Micro y Nanoelectr\u00f3nica, focusing on spintronic devices, neural networks and circuit design with novel topologies, publishing five papers and participating in the design of Ecuador\u00b4s first VLSI microchip. She was also Chair of USFQ\u00b4s 2021 IEEE Student Branch and USFQ\u2019s 2020 Women in Engineering Affinity Group. Ariana has a keen interest in artificial intelligence, computer architecture, and science communication, with a focus on exploring interdisciplinary approaches to the fields of electronics and programming. She is passionate about learning and teaching and, is committed to strengthening the presence of women in STEM.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"

Lecturers March 24 th – March 28 th , 2025Every day from 9 am to 6 pmINAOE, Puebla, M\u00e9xico Victor Grimblatt Victor Grimblatt has an engineering diploma in microelectronics from Institut Nationale Polytechnique de Grenoble (INPG \u2013 France) and an electronic engineering diploma from Universidad Tecnica Federico Santa Maria (Chile). He is doing his PhD […]<\/p>\n","protected":false},"author":2,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"elementor_header_footer","meta":{"_acf_changed":false,"footnotes":""},"class_list":["post-493","page","type-page","status-publish","hentry"],"acf":[],"yoast_head":"\nLecturers - courses<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/asic-chile.cl\/inaoe\/lecturers\/\" \/>\n<meta property=\"og:locale\" content=\"es_ES\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Lecturers - courses\" \/>\n<meta property=\"og:description\" content=\"Lecturers March 24 th – March 28 th , 2025Every day from 9 am to 6 pmINAOE, Puebla, M\u00e9xico Victor Grimblatt Victor Grimblatt has an engineering diploma in microelectronics from Institut Nationale Polytechnique de Grenoble (INPG \u2013 France) and an electronic engineering diploma from Universidad Tecnica Federico Santa Maria (Chile). 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