{"id":16,"date":"2020-01-28T13:44:51","date_gmt":"2020-01-28T13:44:51","guid":{"rendered":"https:\/\/jupiterx.artbees.net\/e-book\/?page_id=16"},"modified":"2024-12-03T13:07:36","modified_gmt":"2024-12-03T13:07:36","slug":"home","status":"publish","type":"page","link":"https:\/\/asic-chile.cl\/academia\/","title":{"rendered":"Home"},"content":{"rendered":"\t\t
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1st Synopsys Chile Digital <\/h1>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Integrated Circuits Design Academy<\/h1>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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January 22th \u2013 March 28th, 2024<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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Every week from 9:00 to 18:00 (working days)

Universidad de La Frontera.

Av. Francisco Salazar 01145, Temuco<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t

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Organizers:<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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Save the date<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Synopsys Chile Digital Integrated Circuits Design Academy Certificate<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Empowering the Next Generation of Semiconductor Professionals<\/b><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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As the technological landscape evolves, semiconductors are the backbone behind new, advanced devices, leading to a growing demand for skilled semiconductor engineers. Deloitte predicts the global industry will need to fill over 1 million additional semiconductor jobs by 2030, equivalent to 100,000 jobs annually, making workforce development programs increasingly vital to modernize our society.<\/p>

Synopsys Chile Innovation Center and Universidad de La Frontera invite you, students in your final year of studies; professionals in electronic, electrical, and computer science engineering; and physics graduates, to participate in the 1st Synopsys Chile Integrated Circuits Design Academy, a 10 week-course where you will attend to classes and workshops enabling access to cutting-edge technologies<\/span> to learn and strengthen skills around design and simulation of digital integrated circuits that are highly demanded in an increasingly more competitive and technologized market.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t

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Rapid changes in Integrated Circuits (IC) technology and constantly shrinking nodes demand new capabilities and skills to meet the contemporary requirements for IC design.<\/strong><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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This course covers the digital IC design flow, from the RTL to the GDSII. All steps of the flow, such as verification, synthesis, place & route, and signoff, will be studied together with practical considered in the corresponding labs. In the last weeks of the academy, students will develop a real project, where they will be able to put into practice the knowledge acquired.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Who should apply?<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t
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Students in their final year of studies; professionals in electronic, electrical, and computer science engineering; and physics graduates.<\/p>

Candidates will be selected based on the background information provided, a knowledge test, and a face-to-face personal interview.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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Synopsys Chile Integrated Circuits Design Academy Certificate<\/a><\/h3>

At the end of the 10-week course participants will receive a certificate and a diploma that certifies the level of knowledge acquired. Certification is granted by Universidad de La Frontera and Synopsys, Inc.<\/p><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t

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Synopsys Scholarships <\/a><\/h3>

There is no cost to participate once you have been selected. In addition, student will receive a total of CLP 750.000 for their 10-weeks participation in order to cover some of their cost of lodging and cost of food.\n<\/p><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Apply now and get certified!<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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*Synopsys Chile<\/b> opened in 2006 is one of Synopsys Inc., most important Innovation centers the company has around the world and the only one in Latin America. Here, more than 170 engineers develop an important part of the latest generation software that the largest global companies use in the design of their chips.<\/p>

**Located in the Region of the Araucan\u00eda, Chile, the Universidad de La Frontera (UFRO)<\/b> is a state, public institution of higher learning, considered among the best universities in the country based on its remarkable indicators of quality and excellence.<\/p>

More information is coming soon.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Preliminar Program <\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
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\u00b7\u00a0\u00a0 \u00a0 \u00a0 <\/span>Unix\/linux (material sent to students)\u200b<\/p>

\u00b7 \u00a0 \u00a0 \u00a0 <\/span>TCL and scripting (material sent to students)\u200b<\/p>

\u00b7\u00a0\u00a0 \u00a0 \u00a0 <\/span>ASIC Design Flow (in person class)<\/p>

\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Basic of CMOS (in person class)\u200b<\/p>

\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Verilog (material sent. to students and in person class)\u200b<\/p>

\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Verilog lab<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t

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RTL and verification (Simulation, coverage, assertion, SAIF)\u200b \u00a0 \u00a0 \u00a0 <\/span>Alejandro Estay<\/p>

\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 System Verilog\u200b \u00a0(<\/span>Alejandro Estay, Wladimir Valenzuela)<\/p>

\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Lab\u200b\u00a0 \u00a0 \u00a0(Alejandro Estay, Wladimir Valenzuela)<\/span><\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t

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\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Synthesis\u200b (Ariana Musello)<\/p>

\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Formality\u200b (Silvia Rinc\u00f3n)<\/p>

\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 DFT\u200b (Ariana Musello, Silvia Rinc\u00f3n)<\/p>

\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Lab\u200b (Silvia Rinc\u00f3n)<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t

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\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Low\u00a0power\u200b (Lucas Santis)<\/p>

\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 STA pre\u00a0layout\u200b (Edward Silva)<\/p>

\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Lab UPF Fundamentals (Sebasti\u00e1n Santelices, Lucas Santis, Edward Silva)<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t

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\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Floorplan\u200b (Jorge Blanco, Ronaldo Serrano)<\/p>

\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Placement\u200b (Jorge Blanco, Ronaldo Serrano)<\/p>

\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Routing\u200b (Jorge Blanco, Ronaldo Serrano)<\/p>

\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Clock tree synthesis\u200b (Jorge Blanco, Ronaldo Serrano)<\/p>

\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Lab\u200b (Jorge Blanco, Ronaldo Serrano)<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t

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\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 STA post layout\u200b (Helmut Rodr\u00edguez, Oscar Araque)<\/p>

\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Sign off\u200b (Helmut Rodr\u00edguez, Oscar Araque)<\/p>

\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Lab\u200b (Helmut Rodr\u00edguez, Oscar Araque)<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t

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\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Review of previous week\u200b (Jos\u00e9 Mart\u00ednez, Andr\u00e9s Centeno)<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t

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\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Project development\u200b<\/p>

\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Project presentation\u200b<\/p>

\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Final exam\u200b<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t

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Lecturers<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t
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Victor Grimblatt<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Victor Grimblatt has an engineering diploma in microelectronics from Institut Nationale Polytechnique de Grenoble (INPG \u2013 France) and an electronic engineering diploma from Universidad Tecnica Federico Santa Maria (Chile). He is doing his PhD on IoT for Smart Agriculture at IMS lab, University of Bordeaux. He is currently R&D Group Director and General Manager of Synopsys Chile. He has expertise and knowledge in business and technology and understands very well the trends of the electronic industry; therefore, he is often consulted for new technological business development. He has published several papers in IoT, EDA and embedded systems development, and since 2007 he has been invited to several Latin American Conferences (Argentina, Brazil, Chile, Mexico, Peru and Uruguay) to talk about Circuit Design, EDA, IoT, and Embedded Systems. Since 2012 he is chair of the IEEE Chilean chapter of the CASS. He is also the President of the Chilean Electronic and Electrical Industry Association (AIE). He has been part of several conferences TCP (ISCAS, ICECS, LASCAS) and is chairing the EDA and Circuit design Sub-Committee for ICECS. He is also Program Co-Chair of FoodCAS. Since 2018 he is Chair of LASCAS Steering Committee.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Ronald Valenzuela<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Ronald Valenzuela currently manages a team of Product Engineers (PE) at Synopsys. With his team, they provide support on Power Optimization and Power Analysis\u202fcapabilities of Synthesis and Place & Route tools. As PEs, they engage with customers to enable methodologies and, also contribute to planning and testing of the tools. Ronald has 10 years of experience in EDA Industry, he is Electronics Engineer of Universidad de Concepci\u00f3n and has a certification on Integrated Circuit design from Stanford University, CA.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Alejandro Estay<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Electronic Engineer from Universidad Catolica de Valparaiso (2019). Previous experience in electronic design for electronic warfare and RF. Working as Applications Engineer for Synopsys since 2022, for Formal Verification products. Digital Design Laboratory Instructor at Universidad Tecnica Federico Santa Maria since 2022 and contributing with teaching material since 2020.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Edward Silva<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Edward Silva received the bachelor\u2019s degree in electronic engineering from Universidad Industrial de Santander (UIS \u2013 Bucaramanga, Colombia) in 2021. In 2017, he was a tutor in an electrical circuit course and from 2019 to 2021, he was part of the Integrated Systems Research Group\u2014OnChip, UIS. He was a Teaching Assistant in the Fundamentals of Analog Circuit course from 2019 to 2021. He is co-author of an IEEE publication as part of his bachelor\u2019s degree project titled \u201cA-Connect: An Ex-Situ Training Methodology to Mitigate Stochasticity in Neural Network Analog Accelerators\u201d. He started to work at Synopsys on March 2022 as Applications Engineer (AE) in the Chile Customer Success Group.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Helmut Rodr\u00edguez<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Electronic Engineer graduated from Universidad Industrial de Santander in Bucaramanga, Colombia, with 1 year of experience in IC Analog design and 2 years of experience in Signoff analysis tools such as (STAR RC, Prime Time, TWEAKER &amp; Prime Closure). With basic knowledge in Parasitic extraction and STA (Static Timing Analysis), a strong focus in the ECO area with tools such as TWEAKER &amp; PrimeClosure. Helmut works as an Applications Engineer for the Customer Success team at Synopsys in Santiago, Chile.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Jorge Blanco<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Jorge is an Electrical Engineer from Universidad de Costa Rica (San Jos\u00e9, Costa Rica). He was working for around 7 years for Componentes Intel de Costa Rica (Intel) in physical\/structural design in the GPU (Graphics Processing Units) area where he was able to develop a highly hands-on experience in Block level and Full-chip Floor-Planning and Layout verification, Route , timing analysis and ECO (Engineering Change Orders) flows, as well knowledge of Synopsys EDA (Electronic Design Automation) tools and Linux scripting skills. Currently, Jorge works as an Applications Engineer for the Customer Success team for Synopsys in Santiago, Chile, providing support to different clients around the world to understanding and improving their workflows and so that the EDA tools they use can provide better performance in their PPA (Power, Performance, Area) metrics. Furthermore, due to his experience, Jorge collaborates in the development and teaching of trainings on physical design, both for his colleagues and Synopsys
collaborations with universities.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Jos\u00e9 Mart\u00ednez<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Jos\u00e9 Mart\u00ednez is an Electrical Engineer with mention in Electronics and Telecommunications, graduated from Universidad de Costa Rica. He holds a master\u2019s degree in Management and Human Resources. Jos\u00e9 started working at Intel Costa Rica in 2014 where he held different roles such as Structural Designer, focusing on thermal analysis, Product Content Validation, centered in Array MBIST DFT, including the pre-silicon and post-silicon verification, repair methodology for redundant SRAMs, NPI (new product introduction), functional content writer for coverage increase, as well as OSNH (Operative System NoHarm) Engineer, in which he was directly involved in platform validation on different soft\/hard reset states, performance, OS and uCode scalability, as well as part of the chip security reactive team. Since 2022 he works at Synopsys Chile. Currently, Jos\u00e9 is part of the CCSG team working towards PPA (power, performance, area) push; improving customers QoR results in a scalable and reproducible methodology.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Oscar Araque<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Electronic engineer with training in software development and design of digital\/analog integrated circuits. Graduated from Universidad Industrial de Santander in Bucaramanga, Colombia, two years of experience in Synopsys supporting Signoff tools. Oscar also collaborates with ECO solutions and tools presentations for application engineers.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Ronaldo Serrano<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Ronaldo Serrano received the B.Sc. degree in electronics from the Universidad Industrial de Santander (UIS) (Bucaramanga-Colombia) in 2020. Besides, a Ph.D. degree in electronics from the University of Electro-Communications (UEC) (Tokyo-Japan) in 2023. He was a Research Assistant in a collaboration between UEC and the National Institute of Advanced Industrial Science and Technology (AIST) focused on hardware for security in Trusted Execution Environments (TEE) based on RISC-V processors from 2020 to 2022. Since 2022, he has been an Applications Engineer at Synopsys in the Chile Customer Success Group (CCSG), providing support in the RTL to GDS process using the fusion compiler tool. He has published several papers related to hardware for security and low-power System on a Chip (SoC). In addition, he serves as an active reviewer in multiple journals like IEEE Access, IEEE Transactions on Circuits and Systems and IEEE transactions on very large-scale integration (VLSI) systems.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Sebasti\u00e1n Santelices<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Sebasti\u00e1n Santelices Herrera is an electric engineer from Pontificia Universidad Cat\u00f3lica (2015) working as Application Engineer for Synopsys since 2016. His line of work is specifically in Design Compiler, Fusion Compiler and IC Compiler II.<\/p>

The topics he is currently working on are related to the use of multivoltage in a circuit and UPF. Unified Power Format (UPF) is the IEEE standard for specifying power intent in power optimization of electronic
design automation.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Silvia Rinc\u00f3n<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Silvia Rinc\u00f3n is an Electronic Engineer from the Universidad Industrial de Santander (UIS \u2013 Bucaramanga, Colombia). She started working at Synopsys Chile as an AE in January 2023 in the CCSG team with the Formality tool. Currently Silvia contributes to the customer in the Formality verification support being able to reproduce the problems of the customer, providing appropriate solutions, as well as the generation of STARs to be passed to R&amp;D support.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Wladimir Valenzuela<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Wladimir Valenzuela is an Electronics Engineer and received his M.Sc. and Ph.D. in Electrical Engineering from the Universidad de Concepci\u00f3n, (Concepci\u00f3n, Chile), with honors. His academic research has focused on the design of low power embedded devices for mixed analog-digital image processing. He has more than 8 years of teaching experience in various university courses related to digital circuits and systems. Wladimir is a Sr. Engineer at Synopsys and leads the Digital Implementation team, which is part of the Chile Customer Success Group (CCSG). The Digital Implementation team focuses on helping customers with the usability of Synopsys tools and collecting feedback to improve them. The team provides support for Fusion Compiler, ICC2, Formality, ICV, among others.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Ariana Musello<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Ariana Musello is an Electronic Engineer with a minor in Computer Science Engineering from Universidad San Francisco de Quito (USFQ), Ecuador. After graduating Summa Cum Laude in 2021 as Valedictorian, she began her career at Synopsys, Chile, as a Test &amp; Validation Engineer in the Design Technology Group. She specializes in automation through creative scripting, infrastructure development to optimize processes, and testing of Synopsys\u2019 EDA tools, with a deep understanding of the integrated circuit design flow. She previously worked as a Research Assistant at USFQ\u2019s Instituto de Micro y Nanoelectr\u00f3nica, focusing on spintronic devices, neural networks and circuit design with novel topologies, publishing five papers and participating in the design of Ecuador\u2019s first VLSI microchip. She was also Chair of USFQ\u2019s 2021 IEEE Student Branch and USFQ\u2019s 2020 Women in Engineering Affinity Group. Ariana has a keen interest in artificial intelligence, computer architecture, and science communication, with a focus on exploring interdisciplinary approaches to the fields of electronics and programming. She is passionate about learning and teaching and, is committed to strengthening the presence of women in STEM.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Victor Grimblatt<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Victor Grimblatt has an engineering diploma in microelectronics from Institut Nationale Polytechnique de Grenoble (INPG \u2013 France) and an electronic engineering diploma from Universidad Tecnica Federico Santa Maria (Chile). He is doing his PhD on IoT for Smart Agriculture at IMS lab, University of Bordeaux. He is currently R&D Group Director and General Manager of Synopsys Chile. He has expertise and knowledge in business and technology and understands very well the trends of the electronic industry; therefore, he is often consulted for new technological business development. He has published several papers in IoT, EDA and embedded systems development, and since 2007 he has been invited to several Latin American Conferences (Argentina, Brazil, Chile, Mexico, Peru and Uruguay) to talk about Circuit Design, EDA, IoT, and Embedded Systems. Since 2012 he is chair of the IEEE Chilean chapter of the CASS. He is also the President of the Chilean Electronic and Electrical Industry Association (AIE). He has been part of several conferences TCP (ISCAS, ICECS, LASCAS) and is chairing the EDA and Circuit design Sub-Committee for ICECS. He is also Program Co-Chair of FoodCAS. Since 2018 he is Chair of LASCAS Steering Committee.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Ronald Valenzuela<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Ronald Valenzuela currently manages a team of Product Engineers (PE) at Synopsys. With his team, they provide support on Power Optimization and Power Analysis\u202fcapabilities of Synthesis and Place & Route tools. As PEs, they engage with customers to enable methodologies and, also contribute to planning and testing of the tools. Ronald has 10 years of experience in EDA Industry, he is Electronics Engineer of Universidad de Concepci\u00f3n and has a certification on Integrated Circuit design from Stanford University, CA.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Alejandro Estay<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Electronic Engineer from Universidad Catolica de Valparaiso (2019). Previous experience in electronic design for electronic warfare and RF. Working as Applications Engineer for Synopsys since 2022, for Formal Verification products. Digital Design Laboratory Instructor at Universidad Tecnica Federico Santa Maria since 2022 and contributing with teaching material since 2020.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Edward Silva<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Edward Silva received the bachelor\u2019s degree in electronic engineering from Universidad Industrial de Santander (UIS \u2013 Bucaramanga, Colombia) in 2021. In 2017, he was a tutor in an electrical circuit course and from 2019 to 2021, he was part of the Integrated Systems Research Group\u2014OnChip, UIS. He was a Teaching Assistant in the Fundamentals of Analog Circuit course from 2019 to 2021. He is co-author of an IEEE publication as part of his bachelor\u2019s degree project titled \u201cA-Connect: An Ex-Situ Training Methodology to Mitigate Stochasticity in Neural Network Analog Accelerators\u201d. He started to work at Synopsys on March 2022 as Applications Engineer (AE) in the Chile Customer Success Group.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Helmut Rodr\u00edguez<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Electronic Engineer graduated from Universidad Industrial de Santander in Bucaramanga, Colombia, with 1 year of experience in IC Analog design and 2 years of experience in Signoff analysis tools such as (STAR RC, Prime Time, TWEAKER &amp; Prime Closure). With basic knowledge in Parasitic extraction and STA (Static Timing Analysis), a strong focus in the ECO area with tools such as TWEAKER &amp; PrimeClosure. Helmut works as an Applications Engineer for the Customer Success team at Synopsys in Santiago, Chile.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Jorge Blanco<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Jorge is an Electrical Engineer from Universidad de Costa Rica (San Jos\u00e9, Costa Rica). He was working for around 7 years for Componentes Intel de Costa Rica (Intel) in physical\/structural design in the GPU (Graphics Processing Units) area where he was able to develop a highly hands-on experience in Block level and Full-chip Floor-Planning and Layout verification, Route , timing analysis and ECO (Engineering Change Orders) flows, as well knowledge of Synopsys EDA (Electronic Design Automation) tools and Linux scripting skills. Currently, Jorge works as an Applications Engineer for the Customer Success team for Synopsys in Santiago, Chile, providing support to different clients around the world to understanding and improving their workflows and so that the EDA tools they use can provide better performance in their PPA (Power, Performance, Area) metrics. Furthermore, due to his experience, Jorge collaborates in the development and teaching of trainings on physical design, both for his colleagues and Synopsys
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Jos\u00e9 Mart\u00ednez<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Jos\u00e9 Mart\u00ednez is an Electrical Engineer with mention in Electronics and Telecommunications, graduated from Universidad de Costa Rica. He holds a master\u2019s degree in Management and Human Resources. Jos\u00e9 started working at Intel Costa Rica in 2014 where he held different roles such as Structural Designer, focusing on thermal analysis, Product Content Validation, centered in Array MBIST DFT, including the pre-silicon and post-silicon verification, repair methodology for redundant SRAMs, NPI (new product introduction), functional content writer for coverage increase, as well as OSNH (Operative System NoHarm) Engineer, in which he was directly involved in platform validation on different soft\/hard reset states, performance, OS and uCode scalability, as well as part of the chip security reactive team. Since 2022 he works at Synopsys Chile. Currently, Jos\u00e9 is part of the CCSG team working towards PPA (power, performance, area) push; improving customers QoR results in a scalable and reproducible methodology.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Oscar Araque<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Electronic engineer with training in software development and design of digital\/analog integrated circuits. Graduated from Universidad Industrial de Santander in Bucaramanga, Colombia, two years of experience in Synopsys supporting Signoff tools. Oscar also collaborates with ECO solutions and tools presentations for application engineers.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Ronaldo Serrano<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Ronaldo Serrano received the B.Sc. degree in electronics from the Universidad Industrial de Santander (UIS) (Bucaramanga-Colombia) in 2020. Besides, a Ph.D. degree in electronics from the University of Electro-Communications (UEC) (Tokyo-Japan) in 2023. He was a Research Assistant in a collaboration between UEC and the National Institute of Advanced Industrial Science and Technology (AIST) focused on hardware for security in Trusted Execution Environments (TEE) based on RISC-V processors from 2020 to 2022. Since 2022, he has been an Applications Engineer at Synopsys in the Chile Customer Success Group (CCSG), providing support in the RTL to GDS process using the fusion compiler tool. He has published several papers related to hardware for security and low-power System on a Chip (SoC). In addition, he serves as an active reviewer in multiple journals like IEEE Access, IEEE Transactions on Circuits and Systems and IEEE transactions on very large-scale integration (VLSI) systems.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Sebasti\u00e1n Santelices<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Sebasti\u00e1n Santelices Herrera is an electric engineer from Pontificia Universidad Cat\u00f3lica (2015) working as Application Engineer for Synopsys since 2016. His line of work is specifically in Design Compiler, Fusion Compiler and IC Compiler II.<\/p>

The topics he is currently working on are related to the use of multivoltage in a circuit and UPF. Unified Power Format (UPF) is the IEEE standard for specifying power intent in power optimization of electronic
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Silvia Rinc\u00f3n<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Silvia Rinc\u00f3n is an Electronic Engineer from the Universidad Industrial de Santander (UIS \u2013 Bucaramanga, Colombia). She started working at Synopsys Chile as an AE in January 2023 in the CCSG team with the Formality tool. Currently Silvia contributes to the customer in the Formality verification support being able to reproduce the problems of the customer, providing appropriate solutions, as well as the generation of STARs to be passed to R&amp;D support.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Wladimir Valenzuela<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Wladimir Valenzuela is an Electronics Engineer and received his M.Sc. and Ph.D. in Electrical Engineering from the Universidad de Concepci\u00f3n, (Concepci\u00f3n, Chile), with honors. His academic research has focused on the design of low power embedded devices for mixed analog-digital image processing. He has more than 8 years of teaching experience in various university courses related to digital circuits and systems. Wladimir is a Sr. Engineer at Synopsys and leads the Digital Implementation team, which is part of the Chile Customer Success Group (CCSG). The Digital Implementation team focuses on helping customers with the usability of Synopsys tools and collecting feedback to improve them. The team provides support for Fusion Compiler, ICC2, Formality, ICV, among others.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Ariana Musello<\/h3><\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Ariana Musello is an Electronic Engineer with a minor in Computer Science Engineering from Universidad San Francisco de Quito (USFQ), Ecuador. After graduating Summa Cum Laude in 2021 as Valedictorian, she began her career at Synopsys, Chile, as a Test &amp; Validation Engineer in the Design Technology Group. She specializes in automation through creative scripting, infrastructure development to optimize processes, and testing of Synopsys\u2019 EDA tools, with a deep understanding of the integrated circuit design flow. She previously worked as a Research Assistant at USFQ\u2019s Instituto de Micro y Nanoelectr\u00f3nica, focusing on spintronic devices, neural networks and circuit design with novel topologies, publishing five papers and participating in the design of Ecuador\u2019s first VLSI microchip. She was also Chair of USFQ\u2019s 2021 IEEE Student Branch and USFQ\u2019s 2020 Women in Engineering Affinity Group. Ariana has a keen interest in artificial intelligence, computer architecture, and science communication, with a focus on exploring interdisciplinary approaches to the fields of electronics and programming. She is passionate about learning and teaching and, is committed to strengthening the presence of women in STEM.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Registration<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t
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PREREQUISITES<\/strong>
Students in their final year of studies; professionals in electronic, electrical, and computer
science engineering; and physics graduates.
Candidates will be selected based on the background information provided, a knowledge test,
and a face-to-face personal interview.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Background information to be attached:<\/p>