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1st Synopsys Chile Digital

Integrated Circuits Design Academy

January 22th – March 28th, 2024

Every week from 9:00 to 18:00 (working days)

Universidad de La Frontera.

Av. Francisco Salazar 01145, Temuco

1st Synopsys Chile

Integrated Circuits Design Academy

January 22th – March 28th, 2024

Every week from 9:00 to 18:00 (working days)

Universidad de La Frontera.

Av. Francisco Salazar 01145, Temuco

Organizers:

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Synopsys Chile Digital Integrated Circuits Design Academy Certificate

Empowering the Next Generation of Semiconductor Professionals

As the technological landscape evolves, semiconductors are the backbone behind new, advanced devices, leading to a growing demand for skilled semiconductor engineers. Deloitte predicts the global industry will need to fill over 1 million additional semiconductor jobs by 2030, equivalent to 100,000 jobs annually, making workforce development programs increasingly vital to modernize our society.

Synopsys Chile Innovation Center and Universidad de La Frontera invite you, students in your final year of studies; professionals in electronic, electrical, and computer science engineering; and physics graduates, to participate in the 1st Synopsys Chile Integrated Circuits Design Academy, a 10 week-course where you will attend to classes and workshops enabling access to cutting-edge technologies to learn and strengthen skills around design and simulation of digital integrated circuits that are highly demanded in an increasingly more competitive and technologized market.

Rapid changes in Integrated Circuits (IC) technology and constantly shrinking nodes demand new capabilities and skills to meet the contemporary requirements for IC design.

This course covers the digital IC design flow, from the RTL to the GDSII. All steps of the flow, such as verification, synthesis, place & route, and signoff, will be studied together with practical considered in the corresponding labs. In the last weeks of the academy, students will develop a real project, where they will be able to put into practice the knowledge acquired.

Who should apply?

Students in their final year of studies; professionals in electronic, electrical, and computer science engineering; and physics graduates.

Candidates will be selected based on the background information provided, a knowledge test, and a face-to-face personal interview.

Synopsys Chile Integrated Circuits Design Academy Certificate

At the end of the 10-week course participants will receive a certificate and a diploma that certifies the level of knowledge acquired. Certification is granted by Universidad de La Frontera and Synopsys, Inc.

Synopsys Scholarships

There is no cost to participate once you have been selected. In addition, student will receive a total of CLP 750.000 for their 10-weeks participation in order to cover some of their cost of lodging and cost of food.

Apply now and get certified!

*Synopsys Chile opened in 2006 is one of Synopsys Inc., most important Innovation centers the company has around the world and the only one in Latin America. Here, more than 170 engineers develop an important part of the latest generation software that the largest global companies use in the design of their chips.

**Located in the Region of the Araucanía, Chile, the Universidad de La Frontera (UFRO) is a state, public institution of higher learning, considered among the best universities in the country based on its remarkable indicators of quality and excellence.

More information is coming soon.

Program

    • Unix/linux (material sent to students)​
    • TCL and scripting (material sent to students)​
    • ASIC Design Flow (in person class)​
    • Basic of CMOS (in person class)​
    • Verilog (material sent. to students and in person class)​
    • Verilog lab​

RTL and verification (Simulation, coverage, assertion, SAIF)​

    • System Verilog​
    • Lab​
    • Synthesis​
    • Formality​
    • DFT​
    • Lab​
    • Low power​
    • STA pre layout​
    • Lab​
    • Floorplan​
    • Placement​
    • Routing​
    • Clock tree synthesis​
    • Lab​
    • STA post layout​
    • Sign off​
    • Lab​
    • Review of previous week​
    • Project development​
    • Project presentation​
    • Final exam​

Week 1

Time
Topic
Lecturer
08:00 – 17:00
Unix/linux (material sent to students)​
TCL and scripting (material sent to students)​
ASIC Design Flow (in person class)​
Basic of CMOS (in person class)​
Verilog (material sent. to students and in person class)​
Verilog lab​

Week 2

Time
Topic
Lecturer
08:00 – 17:00
RTL and verification (Simulation, coverage, assertion, SAIF)​
System Verilog​
Lab​

Week 3

Time
Topic
Lecturer
08:00 – 17:00
Synthesis​
Formality​
DFT​
Lab​

Week 4

Time
Topic
Lecturer
08:00 – 17:00
Low power​
STA pre layout​
Lab​

Week 5

Time
Topic
Lecturer
08:00 – 17:00
Floorplan​
Placement​
Routing​
Clock tree synthesis​
Lab​

Week 6

Time
Topic
Lecturer
08:00 – 17:00
STA post layout​
Sign off​
Lab​

Week 7

Time
Topic
Lecturer
08:00 – 17:00
Review of previous week​

Week 8 -10

Time
Topic
Lecturer
08:00 – 17:00
Project development​
Project presentation​
Final exam​

Some of our Lecturers

Victor-Grimblatt-2.jpg
Víctor Grimblatt
Víctor Grimblatt has an engineering diploma in microelectronics from Institut Nationale Polytechnique de Grenoble (INPG – France) and an electronic engineering diploma from Universidad Tecnica Federico Santa Maria (Chile). He is doing his PhD on IoT for Smart Agriculture at IMS lab, University of Bordeaux. He is currently R&D Group Director and General Manager of Synopsys Chile. He has expertise and knowledge in business and technology and understands very well the trends of the electronic industry; therefore, he is often consulted for new technological business development. He has published several papers in IoT, EDA and embedded systems development, and since 2007 he has been invited to several Latin American Conferences (Argentina, Brazil, Chile, Mexico, Peru and Uruguay) to talk about Circuit Design, EDA, IoT, and Embedded Systems. Since 2012 he is chair of the IEEE Chilean chapter of the CASS. He is also the President of the Chilean Electronic and Electrical Industry Association (AIE). He has been part of several conferences TCP (ISCAS, ICECS, LASCAS) and is chairing the EDA and Circuit design Sub-Committee for ICECS. He is also Program Co-Chair of FoodCAS. Since 2018 he is Chair of LASCAS Steering Committee.
Ronald-Valenzuela.jpg
Ronald Valenzuela
Ronald Valenzuela currently manages a team of Product Engineers (PE) at Synopsys. With his team, they provide support on Power Optimization and Power Analysis capabilities of Synthesis and Place & Route tools. As PEs, they engage with customers to enable methodologies and, also contribute to planning and testing of the tools. Ronald has 10 years of experience in EDA Industry, he is Electronics Engineer of Universidad de Concepción and has a certification on Integrated Circuit design from Stanford University, CA.
Esteban-Viveros-1.jpg
Esteban Viveros
Esteban Viveros is an Electronic Engineer from Universidad de Concepción (Concepcion, Chile). He started to work at Synopsys on December 2013 as Quality Engineer and now he is R&D Manager of a team in Chile Site. The PV team is part of the Digital Design Group (DDG) and works on the “Product Validation” of the Synopsys tools used for RTL Synthesis, Test, Physical Implementation (Place and Route), Formal Verification and Sign-off. His team is responsible of the quality of the tools focusing on the stability, performance, usability and QoR (Quality of Results). The team interacts daily with colleagues and internal/external customers in different parts of the world (mainly US, China and Taiwan). Besides that, Esteban actively collaborates on the university training activities dictated by Synopsys Chile.
Victor-Grimblatt-2.jpg
Víctor Grimblatt
Víctor Grimblatt has an engineering diploma in microelectronics from Institut Nationale Polytechnique de Grenoble (INPG – France) and an electronic engineering diploma from Universidad Tecnica Federico Santa Maria (Chile). He is doing his PhD on IoT for Smart Agriculture at IMS lab, University of Bordeaux. He is currently R&D Group Director and General Manager of Synopsys Chile. He has expertise and knowledge in business and technology and understands very well the trends of the electronic industry; therefore, he is often consulted for new technological business development. He has published several papers in IoT, EDA and embedded systems development, and since 2007 he has been invited to several Latin American Conferences (Argentina, Brazil, Chile, Mexico, Peru and Uruguay) to talk about Circuit Design, EDA, IoT, and Embedded Systems. Since 2012 he is chair of the IEEE Chilean chapter of the CASS. He is also the President of the Chilean Electronic and Electrical Industry Association (AIE). He has been part of several conferences TCP (ISCAS, ICECS, LASCAS) and is chairing the EDA and Circuit design Sub-Committee for ICECS. He is also Program Co-Chair of FoodCAS. Since 2018 he is Chair of LASCAS Steering Committee.
Ronald-Valenzuela.jpg
Ronald Valenzuela
Ronald Valenzuela currently manages a team of Product Engineers (PE) at Synopsys. With his team, they provide support on Power Optimization and Power Analysis capabilities of Synthesis and Place & Route tools. As PEs, they engage with customers to enable methodologies and, also contribute to planning and testing of the tools. Ronald has 10 years of experience in EDA Industry, he is Electronics Engineer of Universidad de Concepción and has a certification on Integrated Circuit design from Stanford University, CA.
Esteban-Viveros-1.jpg
Esteban Viveros
Esteban Viveros is an Electronic Engineer from Universidad de Concepción (Concepcion, Chile). He started to work at Synopsys on December 2013 as Quality Engineer and now he is R&D Manager of a team in Chile Site. The PV team is part of the Digital Design Group (DDG) and works on the “Product Validation” of the Synopsys tools used for RTL Synthesis, Test, Physical Implementation (Place and Route), Formal Verification and Sign-off. His team is responsible of the quality of the tools focusing on the stability, performance, usability and QoR (Quality of Results). The team interacts daily with colleagues and internal/external customers in different parts of the world (mainly US, China and Taiwan). Besides that, Esteban actively collaborates on the university training activities dictated by Synopsys Chile.

Registration (closed)

Students in their final year of studies; professionals in electronic, electrical, and computer science engineering; and physics graduates.

Candidates will be selected based on the background information provided, a knowledge test, and a face-to-face personal interview.

Registration open until December 22, 2023.

 

Background information to be attached:

  • Updated resume
  • Personal letter indicating your motivation to participate
  • Academic backgrounds

Students and graduates: Academic Transcript Certificate

Professionals: Diploma or Degree Certificate.

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