We would like to invite you!

Pontificia Universidad Católica de Valparaíso, IEEE CAS Chile and Synopsys, invites you to the 9th Integrated Circuit Design School. The seminar has lectures and exercise classes where you will be able to design and simulate an IC. Two tracks are available: the Digital track, where you can discover the IC design process (synthesis flow and place-and-route) with Synopsys Design Compiler® and Synopsys IC Compiler® tools; and the analog track, where you wil discover the development process of a small analog circuit, using Synopsys Custom Designer tool®.

January 08



Keynote Lecturers

Keynote Lecturers

Francois Rivet

Associate Professor, IMS Lab and Bordeaux Institute of Technology

Electronics and Mathematics: an introduction to RFIC design

Carlos Silva Cárdenas

Director, Maestria de Ingenieria de las Telecomunicaciones, Pontificia Universidad Católica del Perú

Energy Harvesting

Mauricio Rodríguez Guzman

Associate Professor, Escuela de Ingeniería Eléctrica, Pontificia Universidad Católica de Valparaíso

Modelado del canal inalámbrico para futuras comunicaciones móviles 5G

Ricardo Reis

Associate Professor, Instituto de Informática, Universidade Federal do Rio Grande do Sul

Low Power Challenges in IoT and IoE

School Lecturers

Victor Grimblatt

Managing Director of Synopsys Chile

Ronald Valenzuela

Technical Manager at Synopsys Chile

Esteban Viveros

Supervisor II Quality Engineer at Synopsys Chile

Gonzalo Fernandez

Senior Application Engineer at Synopsys Chile

Registration & Pricing

There are 20 limited vacancies for each track.
The price of the ticket is CLP $20.000. However, you can apply to limited scholarships that cover the registration fee. See the FAQs for more information.
Important: To recieve the confirmation e-mail, you must pay the registration fee first.


School attendants are invited to participate in the technical Poster Session. Poster submission might describe recently completed work, high relevant results of work in progress, or successful system and implementations in areas related to the Circuit design and Systems. Poster submission must be in English, and must include a 2 page abstract plus a draft of the final poster. All submitted material must be in PDF format. Poster format should be A0 (33.1 in x 46.8 in).

If you want to submit a Poster, please inform us that in Registration Form and we will contact you.


Event Partners

Event FAQs

>This summer school is targeted for students and professionals in the areas of Electronic Engineering, Telocommunications, Biomedics, Computer Science, Math, Physics and so, who want to strengthen their knowledge of Integrated Circuit design.

You must have knowledge about basic analog and digital electronics. Programming and Unix skills are not required but desirable.
The ticket includes access to classes, course material, presentations and poster session. Lunch and coffee breaks for each day are also covered, as well as a final cocktail party.
Yes, we have a limited number of scholarships that cover the registration fee. You can apply to them through the registration form, clearly explaining the reasons behind. In case you win a scholarship, the registration fee will be returned back to you at the end of the course.



Av Brasil 2145, 3er Piso
Escuela de Ingeniería Eléctrica, Facultad de Ingeniería
Pontificia Universidad Católica de Valparaíso
Valparaíso, Región de Valparaíso
E-mail: contacto@asic-chile.cl